Lines Matching refs:XD
571 SSEPackedDouble>, XD;
579 SSEPackedDouble>, XD;
1492 XD, VEX, VEX_LIG;
1496 XD, VEX, VEX_W, VEX_LIG;
1524 XD, VEX_4V, VEX_LIG;
1526 XD, VEX_4V, VEX_W, VEX_LIG;
1561 SSE_CVT_SD2SI>, XD;
1564 SSE_CVT_SD2SI>, XD, REX_W;
1573 SSE_CVT_Scalar>, XD;
1576 SSE_CVT_Scalar>, XD, REX_W;
1640 SSE_CVT_SD2SI>, XD, VEX, VEX_LIG;
1643 SSE_CVT_SD2SI>, XD, VEX, VEX_W, VEX_LIG;
1646 sdmem, sse_load_f64, "cvtsd2si", SSE_CVT_SD2SI>, XD;
1648 sdmem, sse_load_f64, "cvtsd2si", SSE_CVT_SD2SI>, XD, REX_W;
1662 SSE_CVT_Scalar, 0>, XD, VEX_4V;
1665 SSE_CVT_Scalar, 0>, XD,
1677 "cvtsi2sd{l}", SSE_CVT_Scalar>, XD;
1680 "cvtsi2sd{q}", SSE_CVT_Scalar>, XD, REX_W;
1698 SSE_CVT_SD2SI>, XD, VEX;
1702 XD, VEX, VEX_W;
1712 SSE_CVT_SD2SI>, XD;
1715 "cvttsd2si", SSE_CVT_SD2SI>, XD, REX_W;
1797 XD, Requires<[HasAVX, OptForSize]>, VEX_4V, VEX_LIG,
1812 XD,
1821 IIC_SSE_CVT_Scalar_RR>, XD, VEX_4V, Requires<[HasAVX]>,
1828 IIC_SSE_CVT_Scalar_RM>, XD, VEX_4V, Requires<[HasAVX]>,
1837 IIC_SSE_CVT_Scalar_RR>, XD, Requires<[UseSSE2]>,
1844 IIC_SSE_CVT_Scalar_RM>, XD, Requires<[UseSSE2]>,
2326 XD, VEX_4V, VEX_LIG;
2336 SSE_ALU_F64S, i8immZExt3>, XD;
2365 XD, VEX_4V;
2373 XD;
3000 XD, VEX_4V, VEX_LIG;
3008 itins.d>, XD;
3019 SSEPackedDouble, itins.d, 0>, XD, VEX_4V, VEX_LIG;
3027 SSEPackedDouble, itins.d>, XD;
3477 OpNode, SSEPackedDouble, itins, UseSSE2, "SD">, XD;
3482 XD, VEX_4V, VEX_LIG;
4273 NoVLX_Or_NoBWI>, XD;
5220 f128mem, SSE_ALU_F32P, loadv4f32, 0>, XD, VEX_4V;
5222 f256mem, SSE_ALU_F32P, loadv8f32, 0>, XD, VEX_4V, VEX_L;
5234 f128mem, SSE_ALU_F32P, memopv4f32>, XD;
7748 imm:$len, imm:$idx))]>, XD;
7753 VR128:$mask))]>, XD;
7763 "movntsd\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVNT>, XD;