Lines Matching full:processor

60   /// X86 processor family: Intel Atom, and others
74   /// True if the processor supports X87 instructions.
77   /// True if this processor has conditional move instructions
81   /// True if the processor supports X86-64 instructions.
84   /// True if the processor supports POPCNT.
87   /// True if the processor supports SSE4A instructions.
120   /// True if the processor has the MOVBE instruction.
123   /// True if the processor has the RDRAND instruction.
126   /// Processor has 16-bit floating point conversion instructions.
129   /// Processor has FS/GS base insturctions.
132   /// Processor has LZCNT instruction.
135   /// Processor has BMI1 instructions.
138   /// Processor has BMI2 instructions.
141   /// Processor has VBMI instructions.
144   /// Processor has Integer Fused Multiply Add
147   /// Processor has RTM instructions.
150   /// Processor has HLE.
153   /// Processor has ADX instructions.
156   /// Processor has SHA instructions.
159   /// Processor has PRFCHW instructions.
162   /// Processor has RDSEED instructions.
165   /// Processor has LAHF/SAHF instructions.
168   /// Processor has MONITORX/MWAITX instructions.
171   /// Processor has Prefetch with intent to Write instruction
187   /// This may require setting a configuration bit in the processor.
190   /// True if this processor has the CMPXCHG16B instruction;
228   /// Processor has AVX-512 PreFetch Instructions
231   /// Processor has AVX-512 Exponential and Reciprocal Instructions
234   /// Processor has AVX-512 Conflict Detection Instructions
237   /// Processor has AVX-512 Doubleword and Quadword instructions
240   /// Processor has AVX-512 Byte and Word instructions
243   /// Processor has AVX-512 Vector Length eXtenstions
246   /// Processor has PKU extenstions
249   /// Processor supports MPX - Memory Protection Extensions
252   /// Processor supports Invalidate Process-Context Identifier
255   /// Processor has VM Functions
258   /// Processor has Supervisor Mode Access Protection
261   /// Processor has Software Guard Extensions
264   /// Processor supports Flush Cache Line instruction
267   /// Processor has Persistent Commit feature
270   /// Processor supports Cache Line Write Back instruction
284   /// What processor and OS we're targeting.
458   /// no-sse2). There isn't any reason to disable it if the target processor