Lines Matching +full:- +full:eq
1 // RUN: llvm-mc -triple thumbv7 -show-encoding < %s | FileCheck %s
3 // Test each of the Thumb1 data-processing instructions
7 // - Rd == Rn
8 // - Rd, Rn and Rm are < r8
11 // - Rd == Rn || Rd == Rm
12 // - Rd, Rn and Rm are < r8
24 IT EQ
25 // CHECK: it eq @ encoding: [0x08,0xbf]
28 IT EQ
29 // CHECK: it eq @ encoding: [0x08,0xbf]
33 IT EQ
34 // CHECK: it eq @ encoding: [0x08,0xbf]
37 IT EQ
38 // CHECK: it eq @ encoding: [0x08,0xbf]
50 IT EQ
51 // CHECK: it eq @ encoding: [0x08,0xbf]
54 IT EQ
55 // CHECK: it eq @ encoding: [0x08,0xbf]
59 IT EQ
60 // CHECK: it eq @ encoding: [0x08,0xbf]
63 IT EQ
64 // CHECK: it eq @ encoding: [0x08,0xbf]
106 ANDS r0, r2, r1 // Must be wide - 3 distinct registers
108 ANDS r2, r1, r2 // Should choose narrow - commutative
111 AND r0, r1, r0 // Must use wide encoding as not flag-setting
118 ANDS r2, r2, r1, lsl #1 // Must use wide - shifted register
135 IT EQ
136 ANDEQ r0, r2, r1 // Must be wide - 3 distinct registers
137 IT EQ
139 IT EQ
140 ANDEQ r3, r1, r3 // Should choose narrow - commutative
141 IT EQ
143 IT EQ
145 IT EQ
146 ANDSEQ r0, r1, r0 // Must use wide encoding as flag-setting
147 IT EQ
149 IT EQ
151 IT EQ
153 IT EQ
155 IT EQ
157 IT EQ
159 IT EQ
160 ANDEQ r0, r0, r1, lsl #1 // Must use wide - shifted register
161 IT EQ
163 // CHECK: it eq @ encoding: [0x08,0xbf]
165 // CHECK: it eq @ encoding: [0x08,0xbf]
167 // CHECK: it eq @ encoding: [0x08,0xbf]
169 // CHECK: it eq @ encoding: [0x08,0xbf]
171 // CHECK: it eq @ encoding: [0x08,0xbf]
173 // CHECK: it eq @ encoding: [0x08,0xbf]
175 // CHECK: it eq @ encoding: [0x08,0xbf]
177 // CHECK: it eq @ encoding: [0x08,0xbf]
179 // CHECK: it eq @ encoding: [0x08,0xbf]
181 // CHECK: it eq @ encoding: [0x08,0xbf]
183 // CHECK: it eq @ encoding: [0x08,0xbf]
185 // CHECK: it eq @ encoding: [0x08,0xbf]
187 // CHECK: it eq @ encoding: [0x08,0xbf]
189 // CHECK: it eq @ encoding: [0x08,0xbf]
193 EORS r0, r2, r1 // Must be wide - 3 distinct registers
195 EORS r5, r1, r5 // Should choose narrow - commutative
198 EOR r1, r1, r1 // Must use wide encoding as not flag-setting
205 EORS r2, r2, r1, lsl #1 // Must use wide - shifted register
222 IT EQ
223 EOREQ r3, r2, r1 // Must be wide - 3 distinct registers
224 IT EQ
226 IT EQ
227 EOREQ r2, r1, r2 // Should choose narrow - commutative
228 IT EQ
230 IT EQ
232 IT EQ
233 EORSEQ r1, r1, r1 // Must use wide encoding as flag-setting
234 IT EQ
236 IT EQ
238 IT EQ
240 IT EQ
242 IT EQ
244 IT EQ
246 IT EQ
247 EOREQ r4, r4, r1, lsl #1 // Must use wide - shifted register
248 IT EQ
250 // CHECK: it eq @ encoding: [0x08,0xbf]
252 // CHECK: it eq @ encoding: [0x08,0xbf]
254 // CHECK: it eq @ encoding: [0x08,0xbf]
256 // CHECK: it eq @ encoding: [0x08,0xbf]
258 // CHECK: it eq @ encoding: [0x08,0xbf]
260 // CHECK: it eq @ encoding: [0x08,0xbf]
262 // CHECK: it eq @ encoding: [0x08,0xbf]
264 // CHECK: it eq @ encoding: [0x08,0xbf]
266 // CHECK: it eq @ encoding: [0x08,0xbf]
268 // CHECK: it eq @ encoding: [0x08,0xbf]
270 // CHECK: it eq @ encoding: [0x08,0xbf]
272 // CHECK: it eq @ encoding: [0x08,0xbf]
274 // CHECK: it eq @ encoding: [0x08,0xbf]
276 // CHECK: it eq @ encoding: [0x08,0xbf]
280 LSLS r0, r2, r1 // Must be wide - 3 distinct registers
282 LSLS r2, r1, r2 // Should choose wide - not commutative
285 LSL r4, r1, r4 // Must use wide encoding as not flag-setting
303 IT EQ
304 LSLEQ r0, r2, r1 // Must be wide - 3 distinct registers
305 IT EQ
307 IT EQ
308 LSLEQ r2, r1, r2 // Should choose wide - not commutative
309 IT EQ
311 IT EQ
313 IT EQ
314 LSLSEQ r4, r1, r4 // Must use wide encoding as flag-setting
315 IT EQ
317 IT EQ
319 IT EQ
321 IT EQ
323 IT EQ
325 // CHECK: it eq @ encoding: [0x08,0xbf]
327 // CHECK: it eq @ encoding: [0x08,0xbf]
329 // CHECK: it eq @ encoding: [0x08,0xbf]
331 // CHECK: it eq @ encoding: [0x08,0xbf]
333 // CHECK: it eq @ encoding: [0x08,0xbf]
335 // CHECK: it eq @ encoding: [0x08,0xbf]
337 // CHECK: it eq @ encoding: [0x08,0xbf]
339 // CHECK: it eq @ encoding: [0x08,0xbf]
341 // CHECK: it eq @ encoding: [0x08,0xbf]
343 // CHECK: it eq @ encoding: [0x08,0xbf]
345 // CHECK: it eq @ encoding: [0x08,0xbf]
349 LSRS r6, r2, r1 // Must be wide - 3 distinct registers
351 LSRS r2, r1, r2 // Should choose wide - not commutative
354 LSR r4, r1, r4 // Must use wide encoding as not flag-setting
372 IT EQ
373 LSREQ r6, r2, r1 // Must be wide - 3 distinct registers
374 IT EQ
376 IT EQ
377 LSREQ r7, r1, r7 // Should choose wide - not commutative
378 IT EQ
380 IT EQ
382 IT EQ
383 LSRSEQ r0, r1, r0 // Must use wide encoding as flag-setting
384 IT EQ
386 IT EQ
388 IT EQ
390 IT EQ
392 IT EQ
394 // CHECK: it eq @ encoding: [0x08,0xbf]
396 // CHECK: it eq @ encoding: [0x08,0xbf]
398 // CHECK: it eq @ encoding: [0x08,0xbf]
400 // CHECK: it eq @ encoding: [0x08,0xbf]
402 // CHECK: it eq @ encoding: [0x08,0xbf]
404 // CHECK: it eq @ encoding: [0x08,0xbf]
406 // CHECK: it eq @ encoding: [0x08,0xbf]
408 // CHECK: it eq @ encoding: [0x08,0xbf]
410 // CHECK: it eq @ encoding: [0x08,0xbf]
412 // CHECK: it eq @ encoding: [0x08,0xbf]
414 // CHECK: it eq @ encoding: [0x08,0xbf]
418 ASRS r7, r6, r5 // Must be wide - 3 distinct registers
420 ASRS r0, r1, r0 // Should choose wide - not commutative
423 ASR r0, r1, r0 // Must use wide encoding as not flag-setting
441 IT EQ
442 ASREQ r0, r2, r1 // Must be wide - 3 distinct registers
443 IT EQ
445 IT EQ
446 ASREQ r1, r2, r1 // Should choose wide - not commutative
447 IT EQ
449 IT EQ
451 IT EQ
452 ASRSEQ r3, r1, r3 // Must use wide encoding as flag-setting
453 IT EQ
455 IT EQ
457 IT EQ
459 IT EQ
461 IT EQ
463 // CHECK: it eq @ encoding: [0x08,0xbf]
465 // CHECK: it eq @ encoding: [0x08,0xbf]
467 // CHECK: it eq @ encoding: [0x08,0xbf]
469 // CHECK: it eq @ encoding: [0x08,0xbf]
471 // CHECK: it eq @ encoding: [0x08,0xbf]
473 // CHECK: it eq @ encoding: [0x08,0xbf]
475 // CHECK: it eq @ encoding: [0x08,0xbf]
477 // CHECK: it eq @ encoding: [0x08,0xbf]
479 // CHECK: it eq @ encoding: [0x08,0xbf]
481 // CHECK: it eq @ encoding: [0x08,0xbf]
483 // CHECK: it eq @ encoding: [0x08,0xbf]
487 ADCS r5, r2, r1 // Must be wide - 3 distinct registers
489 ADCS r3, r1, r3 // Should choose narrow - commutative
492 ADC r0, r1, r0 // Must use wide encoding as not flag-setting
499 ADCS r3, r3, r1, lsl #1 // Must use wide - shifted register
516 IT EQ
517 ADCEQ r1, r2, r3 // Must be wide - 3 distinct registers
518 IT EQ
520 IT EQ
521 ADCEQ r3, r1, r3 // Should choose narrow - commutative
522 IT EQ
524 IT EQ
526 IT EQ
527 ADCSEQ r3, r1, r3 // Must use wide encoding as flag-setting
528 IT EQ
530 IT EQ
532 IT EQ
534 IT EQ
536 IT EQ
538 IT EQ
540 IT EQ
541 ADCEQ r2, r2, r1, lsl #1 // Must use wide - shifted register
542 IT EQ
544 // CHECK: it eq @ encoding: [0x08,0xbf]
546 // CHECK: it eq @ encoding: [0x08,0xbf]
548 // CHECK: it eq @ encoding: [0x08,0xbf]
550 // CHECK: it eq @ encoding: [0x08,0xbf]
552 // CHECK: it eq @ encoding: [0x08,0xbf]
554 // CHECK: it eq @ encoding: [0x08,0xbf]
556 // CHECK: it eq @ encoding: [0x08,0xbf]
558 // CHECK: it eq @ encoding: [0x08,0xbf]
560 // CHECK: it eq @ encoding: [0x08,0xbf]
562 // CHECK: it eq @ encoding: [0x08,0xbf]
564 // CHECK: it eq @ encoding: [0x08,0xbf]
566 // CHECK: it eq @ encoding: [0x08,0xbf]
568 // CHECK: it eq @ encoding: [0x08,0xbf]
570 // CHECK: it eq @ encoding: [0x08,0xbf]
574 SBCS r3, r2, r1 // Must be wide - 3 distinct registers
576 SBCS r1, r4, r1 // Should choose wide - not commutative
579 SBC r0, r1, r0 // Must use wide encoding as not flag-setting
585 SBCS r2, r2, r1, lsl #1 // Must use wide - shifted register
601 IT EQ
602 SBCEQ r5, r2, r1 // Must be wide - 3 distinct registers
603 IT EQ
605 IT EQ
607 IT EQ
609 IT EQ
611 IT EQ
612 SBCSEQ r2, r1, r2 // Must use wide encoding as flag-setting
613 IT EQ
615 IT EQ
617 IT EQ
619 IT EQ
621 IT EQ
623 IT EQ
624 SBCEQ r2, r2, r1, lsl #1 // Must use wide - shifted register
625 IT EQ
627 // CHECK: it eq @ encoding: [0x08,0xbf]
629 // CHECK: it eq @ encoding: [0x08,0xbf]
631 // CHECK: it eq @ encoding: [0x08,0xbf]
633 // CHECK: it eq @ encoding: [0x08,0xbf]
635 // CHECK: it eq @ encoding: [0x08,0xbf]
637 // CHECK: it eq @ encoding: [0x08,0xbf]
639 // CHECK: it eq @ encoding: [0x08,0xbf]
641 // CHECK: it eq @ encoding: [0x08,0xbf]
643 // CHECK: it eq @ encoding: [0x08,0xbf]
645 // CHECK: it eq @ encoding: [0x08,0xbf]
647 // CHECK: it eq @ encoding: [0x08,0xbf]
649 // CHECK: it eq @ encoding: [0x08,0xbf]
651 // CHECK: it eq @ encoding: [0x08,0xbf]
655 RORS r3, r2, r1 // Must be wide - 3 distinct registers
657 RORS r1, r0, r1 // Should choose wide - not commutative
660 ROR r5, r1, r5 // Must use wide encoding as not flag-setting
678 IT EQ
679 ROREQ r4, r2, r1 // Must be wide - 3 distinct registers
680 IT EQ
682 IT EQ
683 ROREQ r1, r4, r1 // Should choose wide - not commutative
684 IT EQ
686 IT EQ
688 IT EQ
689 RORSEQ r0, r1, r0 // Must use wide encoding as flag-setting
690 IT EQ
692 IT EQ
694 IT EQ
696 IT EQ
698 IT EQ
700 // CHECK: it eq @ encoding: [0x08,0xbf]
702 // CHECK: it eq @ encoding: [0x08,0xbf]
704 // CHECK: it eq @ encoding: [0x08,0xbf]
706 // CHECK: it eq @ encoding: [0x08,0xbf]
708 // CHECK: it eq @ encoding: [0x08,0xbf]
710 // CHECK: it eq @ encoding: [0x08,0xbf]
712 // CHECK: it eq @ encoding: [0x08,0xbf]
714 // CHECK: it eq @ encoding: [0x08,0xbf]
716 // CHECK: it eq @ encoding: [0x08,0xbf]
718 // CHECK: it eq @ encoding: [0x08,0xbf]
720 // CHECK: it eq @ encoding: [0x08,0xbf]
723 // TST - only two register version available
724 // RSB - only two register version available
725 // CMP - only two register version available
726 // CMN - only two register version available
729 ORRS r7, r2, r1 // Must be wide - 3 distinct registers
731 ORRS r3, r1, r3 // Should choose narrow - commutative
734 ORR r2, r1, r2 // Must use wide encoding as not flag-setting
741 ORRS r1, r1, r1, lsl #1 // Must use wide - shifted register
758 IT EQ
759 ORREQ r0, r2, r1 // Must be wide - 3 distinct registers
760 IT EQ
762 IT EQ
763 ORREQ r5, r1, r5 // Should choose narrow - commutative
764 IT EQ
766 IT EQ
768 IT EQ
769 ORRSEQ r4, r1, r4 // Must use wide encoding as flag-setting
770 IT EQ
772 IT EQ
774 IT EQ
776 IT EQ
778 IT EQ
780 IT EQ
782 IT EQ
783 ORREQ r2, r2, r1, lsl #1 // Must use wide - shifted register
784 IT EQ
786 // CHECK: it eq @ encoding: [0x08,0xbf]
788 // CHECK: it eq @ encoding: [0x08,0xbf]
790 // CHECK: it eq @ encoding: [0x08,0xbf]
792 // CHECK: it eq @ encoding: [0x08,0xbf]
794 // CHECK: it eq @ encoding: [0x08,0xbf]
796 // CHECK: it eq @ encoding: [0x08,0xbf]
798 // CHECK: it eq @ encoding: [0x08,0xbf]
800 // CHECK: it eq @ encoding: [0x08,0xbf]
802 // CHECK: it eq @ encoding: [0x08,0xbf]
804 // CHECK: it eq @ encoding: [0x08,0xbf]
806 // CHECK: it eq @ encoding: [0x08,0xbf]
808 // CHECK: it eq @ encoding: [0x08,0xbf]
810 // CHECK: it eq @ encoding: [0x08,0xbf]
812 // CHECK: it eq @ encoding: [0x08,0xbf]
815 // MUL - not affected by this change
818 BICS r3, r2, r1 // Must be wide - 3 distinct registers
820 BICS r1, r2, r1 // Should choose wide - not commutative
823 BIC r0, r1, r0 // Must use wide encoding as not flag-setting
829 BICS r3, r3, r1, lsl #1 // Must use wide - shifted register
845 IT EQ
846 BICEQ r0, r2, r1 // Must be wide - 3 distinct registers
847 IT EQ
849 IT EQ
850 BICEQ r1, r5, r1 // Should choose wide - not commutative
851 IT EQ
853 IT EQ
855 IT EQ
856 BICSEQ r5, r1, r5 // Must use wide encoding as flag-setting
857 IT EQ
859 IT EQ
861 IT EQ
863 IT EQ
865 IT EQ
867 IT EQ
868 BICEQ r4, r4, r1, lsl #1 // Must use wide - shifted register
869 IT EQ
871 // CHECK: it eq @ encoding: [0x08,0xbf]
873 // CHECK: it eq @ encoding: [0x08,0xbf]
875 // CHECK: it eq @ encoding: [0x08,0xbf]
877 // CHECK: it eq @ encoding: [0x08,0xbf]
879 // CHECK: it eq @ encoding: [0x08,0xbf]
881 // CHECK: it eq @ encoding: [0x08,0xbf]
883 // CHECK: it eq @ encoding: [0x08,0xbf]
885 // CHECK: it eq @ encoding: [0x08,0xbf]
887 // CHECK: it eq @ encoding: [0x08,0xbf]
889 // CHECK: it eq @ encoding: [0x08,0xbf]
891 // CHECK: it eq @ encoding: [0x08,0xbf]
893 // CHECK: it eq @ encoding: [0x08,0xbf]
895 // CHECK: it eq @ encoding: [0x08,0xbf]
898 // CMN - only two register version available