Lines Matching refs:pTileInfo
142 const ADDR_TILEINFO* pTileInfo ///< [in] Tile info in HwlGetPipes()
147 if (pTileInfo) in HwlGetPipes()
149 numPipes = GetPipePerSurf(pTileInfo->pipeConfig); in HwlGetPipes()
221 ADDR_TILEINFO* pTileInfo, ///< [in] tile info in ComputeBankEquation() argument
227 UINT_32 pipes = HwlGetPipes(pTileInfo); in ComputeBankEquation()
228 UINT_32 bankXStart = 3 + Log2(pipes) + Log2(pTileInfo->bankWidth); in ComputeBankEquation()
229 UINT_32 bankYStart = 3 + Log2(pTileInfo->bankHeight); in ComputeBankEquation()
249 switch (pTileInfo->banks) in ComputeBankEquation()
252 if (pTileInfo->macroAspectRatio == 1) in ComputeBankEquation()
264 else if (pTileInfo->macroAspectRatio == 2) in ComputeBankEquation()
276 else if (pTileInfo->macroAspectRatio == 4) in ComputeBankEquation()
288 else if (pTileInfo->macroAspectRatio == 8) in ComputeBankEquation()
307 if (pTileInfo->macroAspectRatio == 1) in ComputeBankEquation()
317 else if (pTileInfo->macroAspectRatio == 2) in ComputeBankEquation()
327 else if (pTileInfo->macroAspectRatio == 4) in ComputeBankEquation()
344 if (pTileInfo->macroAspectRatio == 1) in ComputeBankEquation()
351 else if (pTileInfo->macroAspectRatio == 2) in ComputeBankEquation()
368 if (pTileInfo->macroAspectRatio == 1) in ComputeBankEquation()
425 if ((pTileInfo->bankWidth == 1) && in ComputeBankEquation()
426 ((pTileInfo->pipeConfig == ADDR_PIPECFG_P4_32x32) || in ComputeBankEquation()
427 (pTileInfo->pipeConfig == ADDR_PIPECFG_P8_32x64_32x32))) in ComputeBankEquation()
450 ADDR_TILEINFO* pTileInfo, ///< [in] Tile info in ComputePipeEquation() argument
478 switch (pTileInfo->pipeConfig) in ComputePipeEquation()
650 ADDR_TILEINFO* pTileInfo ///< [in] Tile info in ComputePipeFromCoord()
672 switch (pTileInfo->pipeConfig) in ComputePipeFromCoord()
1195 ADDR_TILEINFO* pTileInfo ///< [in] tile info in HwlComputeTileDataWidthAndHeightLinear()
1198 ADDR_ASSERT(pTileInfo != NULL); in HwlComputeTileDataWidthAndHeightLinear()
1206 if ((pTileInfo->pipeConfig == ADDR_PIPECFG_P8_32x64_32x32) || in HwlComputeTileDataWidthAndHeightLinear()
1207 (pTileInfo->pipeConfig == ADDR_PIPECFG_P16_32x32_8x16) || in HwlComputeTileDataWidthAndHeightLinear()
1208 (pTileInfo->pipeConfig == ADDR_PIPECFG_P8_32x32_16x16)) in HwlComputeTileDataWidthAndHeightLinear()
1268 ADDR_TILEINFO* pTileInfo, ///< [in] Tile info in HwlComputeXmaskAddrFromCoord() argument
1295 pTileInfo, in HwlComputeXmaskAddrFromCoord()
1316 pTileInfo, in HwlComputeXmaskAddrFromCoord()
1338 TileCoordToMaskElementIndex(tx, ty, pTileInfo->pipeConfig, µShift, &elemIdxBits); in HwlComputeXmaskAddrFromCoord()
1340 UINT_32 numPipes = HwlGetPipes(pTileInfo); in HwlComputeXmaskAddrFromCoord()
1392 UINT_32 pipe = ComputePipeFromCoord(x, y, 0, ADDR_TM_2D_TILED_THIN1, 0, FALSE, pTileInfo); in HwlComputeXmaskAddrFromCoord()
1426 ADDR_TILEINFO* pTileInfo, ///< [in] Tile info in HwlComputeXmaskCoordFromAddr() argument
1455 pTileInfo, in HwlComputeXmaskCoordFromAddr()
1475 pTileInfo, in HwlComputeXmaskCoordFromAddr()
1490 TileCoordToMaskElementIndex(0, 0, pTileInfo->pipeConfig, ¯oShift, &elemIdxBits); in HwlComputeXmaskCoordFromAddr()
1492 const UINT_32 numPipes = HwlGetPipes(pTileInfo); in HwlComputeXmaskCoordFromAddr()
1551 switch (pTileInfo->pipeConfig) in HwlComputeXmaskCoordFromAddr()
1569 if (pTileInfo->pipeConfig == ADDR_PIPECFG_P8_32x64_32x32) in HwlComputeXmaskCoordFromAddr()
1573 if((pTileInfo->pipeConfig == ADDR_PIPECFG_P16_32x32_8x16) || in HwlComputeXmaskCoordFromAddr()
1574 (pTileInfo->pipeConfig == ADDR_PIPECFG_P16_32x32_16x16)) in HwlComputeXmaskCoordFromAddr()
1601 ComputeTileCoordFromPipeAndElemIdx(elemIdx, pipe, pTileInfo->pipeConfig, pitchInMacroTile, in HwlComputeXmaskCoordFromAddr()
1928 ADDR_TILEINFO* pTileInfo = pTileInfoOut; in HwlSetupTileInfo() local
1949 if (IsTileInfoAllZero(pTileInfo)) in HwlSetupTileInfo()
2202 *pTileInfo = m_tileTable[index].info; in HwlSetupTileInfo()
2208 *pTileInfo = m_tileTable[8].info; in HwlSetupTileInfo()
2219 *pTileInfo = m_tileTable[0].info; in HwlSetupTileInfo()
2390 if (pIn->pTileInfo->pipeConfig == ADDR_PIPECFG_INVALID) in HwlConvertTileInfoToHW()
2396 pOut->pTileInfo->pipeConfig = in HwlConvertTileInfoToHW()
2397 static_cast<AddrPipeCfg>(pIn->pTileInfo->pipeConfig - 1); in HwlConvertTileInfoToHW()
2402 pOut->pTileInfo->pipeConfig = in HwlConvertTileInfoToHW()
2403 static_cast<AddrPipeCfg>(pIn->pTileInfo->pipeConfig + 1); in HwlConvertTileInfoToHW()
2454 ADDR_TILEINFO* pTileInfo ///< [in] bank structure. **All fields to be valid on entry** in HwlComputeSurfaceCoord2DFromBankPipe()
2468 UINT_32 numPipes = GetPipePerSurf(pTileInfo->pipeConfig); in HwlComputeSurfaceCoord2DFromBankPipe()
2472 bankSwizzle, pipeSwizzle, tileSlices, pTileInfo, in HwlComputeSurfaceCoord2DFromBankPipe()
2487 if ((pTileInfo->pipeConfig == ADDR_PIPECFG_P4_32x32) || in HwlComputeSurfaceCoord2DFromBankPipe()
2488 (pTileInfo->pipeConfig == ADDR_PIPECFG_P8_32x64_32x32)) in HwlComputeSurfaceCoord2DFromBankPipe()
2490 ADDR_ASSERT(pTileInfo->bankWidth == 1 && pTileInfo->macroAspectRatio > 1); in HwlComputeSurfaceCoord2DFromBankPipe()
2491 UINT_32 yBitToCheck = QLog2(pTileInfo->banks) - 1; in HwlComputeSurfaceCoord2DFromBankPipe()
2503 *pY += yBit * pTileInfo->bankHeight * MicroTileHeight; in HwlComputeSurfaceCoord2DFromBankPipe()
2504 *pX += xBit * numPipes * pTileInfo->bankWidth * MicroTileWidth; in HwlComputeSurfaceCoord2DFromBankPipe()
2527 switch (pTileInfo->pipeConfig) in HwlComputeSurfaceCoord2DFromBankPipe()
2611 ADDR_TILEINFO* pTileInfo ///< [in] tile info in HwlPreAdjustBank()
2614 if (((pTileInfo->pipeConfig == ADDR_PIPECFG_P4_32x32) || in HwlPreAdjustBank()
2615 (pTileInfo->pipeConfig == ADDR_PIPECFG_P8_32x64_32x32)) && (pTileInfo->bankWidth == 1)) in HwlPreAdjustBank()
2624 ADDR_ASSERT(pTileInfo->macroAspectRatio > 1); in HwlPreAdjustBank()
2801 pOut->pTileInfo); in HwlCheckLastMacroTiledLvl()
3137 pOut->index = HwlPostCheckTileIndex(pIn->pTileInfo, pIn->tileMode, pIn->tileType); in HwlGetTileIndex()
3668 const ADDR_TILEINFO* pTileInfo = &tileConfig.info; in InitEquationTable() local
3671 HwlGetPipes(pTileInfo) * MicroTileWidth * pTileInfo->bankWidth * in InitEquationTable()
3672 pTileInfo->macroAspectRatio; in InitEquationTable()
3674 MicroTileHeight * pTileInfo->bankHeight * pTileInfo->banks / in InitEquationTable()
3675 pTileInfo->macroAspectRatio; in InitEquationTable()
3747 const ADDR_TILEINFO* pTileInfo = &tileConfig.info; in InitEquationTable() local
3750 HwlGetPipes(pTileInfo) * MicroTileWidth * pTileInfo->bankWidth * in InitEquationTable()
3751 pTileInfo->macroAspectRatio; in InitEquationTable()
3753 MicroTileHeight * pTileInfo->bankHeight * pTileInfo->banks / in InitEquationTable()
3754 pTileInfo->macroAspectRatio; in InitEquationTable()