Lines Matching refs:qinst
76 static struct qinst *
80 struct qinst *qinst = vir_add_inst(V3D_QPU_A_NOP, undef, undef, undef); in vir_nop() local
82 return qinst; in vir_nop()
85 static struct qinst *
86 new_qpu_nop_before(struct qinst *inst) in new_qpu_nop_before()
88 struct qinst *q = vir_nop(); in new_qpu_nop_before()
96 new_ldunif_instr(struct qinst *inst, int i) in new_ldunif_instr()
98 struct qinst *ldunif = new_qpu_nop_before(inst); in new_ldunif_instr()
148 vir_for_each_inst(qinst, block) { in v3d_generate_code_block()
151 vir_dump_inst(c, qinst); in v3d_generate_code_block()
155 struct qinst *temp; in v3d_generate_code_block()
157 if (vir_has_implicit_uniform(qinst)) { in v3d_generate_code_block()
158 int src = vir_get_implicit_uniform_src(qinst); in v3d_generate_code_block()
159 assert(qinst->src[src].file == QFILE_UNIF); in v3d_generate_code_block()
160 qinst->uniform = qinst->src[src].index; in v3d_generate_code_block()
164 int nsrc = vir_get_non_sideband_nsrc(qinst); in v3d_generate_code_block()
165 struct qpu_reg src[ARRAY_SIZE(qinst->src)]; in v3d_generate_code_block()
168 int index = qinst->src[i].index; in v3d_generate_code_block()
169 switch (qinst->src[i].file) { in v3d_generate_code_block()
171 src[i] = qpu_reg(qinst->src[i].index); in v3d_generate_code_block()
174 src[i] = qpu_magic(qinst->src[i].index); in v3d_generate_code_block()
185 new_ldunif_instr(qinst, i); in v3d_generate_code_block()
196 src[i].addr = qpu_encode_small_immediate(qinst->src[i].index); in v3d_generate_code_block()
205 assert((int)qinst->src[i].index >= in v3d_generate_code_block()
208 last_vpm_read_index = qinst->src[i].index; in v3d_generate_code_block()
210 temp = new_qpu_nop_before(qinst); in v3d_generate_code_block()
223 switch (qinst->dst.file) { in v3d_generate_code_block()
229 dst = qpu_reg(qinst->dst.index); in v3d_generate_code_block()
233 dst = qpu_magic(qinst->dst.index); in v3d_generate_code_block()
237 dst = temp_registers[qinst->dst.index]; in v3d_generate_code_block()
259 if (qinst->qpu.type == V3D_QPU_INSTR_TYPE_ALU) { in v3d_generate_code_block()
261 &qinst->qpu.sig)) { in v3d_generate_code_block()
262 assert(qinst->qpu.alu.add.op == V3D_QPU_A_NOP); in v3d_generate_code_block()
263 assert(qinst->qpu.alu.mul.op == V3D_QPU_M_NOP); in v3d_generate_code_block()
265 qinst->qpu.sig_addr = dst.index; in v3d_generate_code_block()
266 qinst->qpu.sig_magic = dst.magic; in v3d_generate_code_block()
267 } else if (qinst->qpu.alu.add.op != V3D_QPU_A_NOP) { in v3d_generate_code_block()
268 assert(qinst->qpu.alu.mul.op == V3D_QPU_M_NOP); in v3d_generate_code_block()
270 set_src(&qinst->qpu, in v3d_generate_code_block()
271 &qinst->qpu.alu.add.a, src[0]); in v3d_generate_code_block()
274 set_src(&qinst->qpu, in v3d_generate_code_block()
275 &qinst->qpu.alu.add.b, src[1]); in v3d_generate_code_block()
278 qinst->qpu.alu.add.waddr = dst.index; in v3d_generate_code_block()
279 qinst->qpu.alu.add.magic_write = dst.magic; in v3d_generate_code_block()
282 set_src(&qinst->qpu, in v3d_generate_code_block()
283 &qinst->qpu.alu.mul.a, src[0]); in v3d_generate_code_block()
286 set_src(&qinst->qpu, in v3d_generate_code_block()
287 &qinst->qpu.alu.mul.b, src[1]); in v3d_generate_code_block()
290 qinst->qpu.alu.mul.waddr = dst.index; in v3d_generate_code_block()
291 qinst->qpu.alu.mul.magic_write = dst.magic; in v3d_generate_code_block()
294 assert(qinst->qpu.type == V3D_QPU_INSTR_TYPE_BRANCH); in v3d_generate_code_block()