929                  const struct v3d_qpu_instr *instr, uint64_t *packed_instr)  in v3d_qpu_add_pack()  argument
984                 *packed_instr |= VC5_QPU_MA;  in v3d_qpu_add_pack()
1108         *packed_instr |= QPU_SET_FIELD(mux_a, VC5_QPU_ADD_A);  in v3d_qpu_add_pack()
1109         *packed_instr |= QPU_SET_FIELD(mux_b, VC5_QPU_ADD_B);  in v3d_qpu_add_pack()
1110         *packed_instr |= QPU_SET_FIELD(opcode, VC5_QPU_OP_ADD);  in v3d_qpu_add_pack()
1111         *packed_instr |= QPU_SET_FIELD(waddr, V3D_QPU_WADDR_A);  in v3d_qpu_add_pack()
1113                 *packed_instr |= VC5_QPU_MA;  in v3d_qpu_add_pack()
1120                  const struct v3d_qpu_instr *instr, uint64_t *packed_instr)  in v3d_qpu_mul_pack()  argument
1216         *packed_instr |= QPU_SET_FIELD(mux_a, VC5_QPU_MUL_A);  in v3d_qpu_mul_pack()
1217         *packed_instr |= QPU_SET_FIELD(mux_b, VC5_QPU_MUL_B);  in v3d_qpu_mul_pack()
1219         *packed_instr |= QPU_SET_FIELD(opcode, VC5_QPU_OP_MUL);  in v3d_qpu_mul_pack()
1220         *packed_instr |= QPU_SET_FIELD(instr->alu.mul.waddr, V3D_QPU_WADDR_M);  in v3d_qpu_mul_pack()
1222                 *packed_instr |= VC5_QPU_MM;  in v3d_qpu_mul_pack()
1229                          uint64_t packed_instr,  in v3d_qpu_instr_unpack_alu()  argument
1235                                 QPU_GET_FIELD(packed_instr, VC5_QPU_SIG),  in v3d_qpu_instr_unpack_alu()
1239         uint32_t packed_cond = QPU_GET_FIELD(packed_instr, VC5_QPU_COND);  in v3d_qpu_instr_unpack_alu()
1255         instr->raddr_a = QPU_GET_FIELD(packed_instr, VC5_QPU_RADDR_A);  in v3d_qpu_instr_unpack_alu()
1256         instr->raddr_b = QPU_GET_FIELD(packed_instr, VC5_QPU_RADDR_B);  in v3d_qpu_instr_unpack_alu()
1258         if (!v3d_qpu_add_unpack(devinfo, packed_instr, instr))  in v3d_qpu_instr_unpack_alu()
1261         if (!v3d_qpu_mul_unpack(devinfo, packed_instr, instr))  in v3d_qpu_instr_unpack_alu()
1269                             uint64_t packed_instr,  in v3d_qpu_instr_unpack_branch()  argument
1274         uint32_t cond = QPU_GET_FIELD(packed_instr, VC5_QPU_BRANCH_COND);  in v3d_qpu_instr_unpack_branch()
1283         uint32_t msfign = QPU_GET_FIELD(packed_instr, VC5_QPU_BRANCH_MSFIGN);  in v3d_qpu_instr_unpack_branch()
1288         instr->branch.bdi = QPU_GET_FIELD(packed_instr, VC5_QPU_BRANCH_BDI);  in v3d_qpu_instr_unpack_branch()
1290         instr->branch.ub = packed_instr & VC5_QPU_BRANCH_UB;  in v3d_qpu_instr_unpack_branch()
1292                 instr->branch.bdu = QPU_GET_FIELD(packed_instr,  in v3d_qpu_instr_unpack_branch()
1296         instr->branch.raddr_a = QPU_GET_FIELD(packed_instr,  in v3d_qpu_instr_unpack_branch()
1302                 QPU_GET_FIELD(packed_instr,  in v3d_qpu_instr_unpack_branch()
1306                 QPU_GET_FIELD(packed_instr,  in v3d_qpu_instr_unpack_branch()
1314                      uint64_t packed_instr,  in v3d_qpu_instr_unpack()  argument
1317         if (QPU_GET_FIELD(packed_instr, VC5_QPU_OP_MUL) != 0) {  in v3d_qpu_instr_unpack()
1318                 return v3d_qpu_instr_unpack_alu(devinfo, packed_instr, instr);  in v3d_qpu_instr_unpack()
1320                 uint32_t sig = QPU_GET_FIELD(packed_instr, VC5_QPU_SIG);  in v3d_qpu_instr_unpack()
1323                         return v3d_qpu_instr_unpack_branch(devinfo, packed_instr,  in v3d_qpu_instr_unpack()
1334                        uint64_t *packed_instr)  in v3d_qpu_instr_pack_alu()  argument
1339         *packed_instr |= QPU_SET_FIELD(sig, VC5_QPU_SIG);  in v3d_qpu_instr_pack_alu()
1342                 *packed_instr |= QPU_SET_FIELD(instr->raddr_a, VC5_QPU_RADDR_A);  in v3d_qpu_instr_pack_alu()
1343                 *packed_instr |= QPU_SET_FIELD(instr->raddr_b, VC5_QPU_RADDR_B);  in v3d_qpu_instr_pack_alu()
1345                 if (!v3d_qpu_add_pack(devinfo, instr, packed_instr))  in v3d_qpu_instr_pack_alu()
1347                 if (!v3d_qpu_mul_pack(devinfo, instr, packed_instr))  in v3d_qpu_instr_pack_alu()
1369                 *packed_instr |= QPU_SET_FIELD(flags, VC5_QPU_COND);  in v3d_qpu_instr_pack_alu()
1381                           uint64_t *packed_instr)  in v3d_qpu_instr_pack_branch()  argument
1383         *packed_instr |= QPU_SET_FIELD(16, VC5_QPU_SIG);  in v3d_qpu_instr_pack_branch()
1386                 *packed_instr |= QPU_SET_FIELD(2 + (instr->branch.cond -  in v3d_qpu_instr_pack_branch()
1391         *packed_instr |= QPU_SET_FIELD(instr->branch.msfign,  in v3d_qpu_instr_pack_branch()
1394         *packed_instr |= QPU_SET_FIELD(instr->branch.bdi,  in v3d_qpu_instr_pack_branch()
1398                 *packed_instr |= VC5_QPU_BRANCH_UB;  in v3d_qpu_instr_pack_branch()
1399                 *packed_instr |= QPU_SET_FIELD(instr->branch.bdu,  in v3d_qpu_instr_pack_branch()
1406                 *packed_instr |= QPU_SET_FIELD(instr->branch.msfign,  in v3d_qpu_instr_pack_branch()
1409                 *packed_instr |= QPU_SET_FIELD((instr->branch.offset &  in v3d_qpu_instr_pack_branch()
1413                 *packed_instr |= QPU_SET_FIELD(instr->branch.offset >> 24,  in v3d_qpu_instr_pack_branch()
1417                 *packed_instr |= QPU_SET_FIELD(instr->branch.raddr_a,  in v3d_qpu_instr_pack_branch()
1431                    uint64_t *packed_instr)  in v3d_qpu_instr_pack()  argument
1433         *packed_instr = 0;  in v3d_qpu_instr_pack()
1437                 return v3d_qpu_instr_pack_alu(devinfo, instr, packed_instr);  in v3d_qpu_instr_pack()
1439                 return v3d_qpu_instr_pack_branch(devinfo, instr, packed_instr);  in v3d_qpu_instr_pack()