Lines Matching refs:legacy
220 assert(rtex->surface.u.legacy.level[level].dcc_fast_clear_size); in vi_dcc_clear_level()
227 dcc_offset += rtex->surface.u.legacy.level[level].dcc_offset; in vi_dcc_clear_level()
228 clear_size = rtex->surface.u.legacy.level[level].dcc_fast_clear_size * in vi_dcc_clear_level()
249 rtex->surface.u.legacy.level[0].mode == RADEON_SURF_MODE_2D); in si_set_optimal_micro_tile_mode()
290 rtex->surface.u.legacy.tiling_index[0] = 10; in si_set_optimal_micro_tile_mode()
293 rtex->surface.u.legacy.tiling_index[0] = 14; in si_set_optimal_micro_tile_mode()
296 rtex->surface.u.legacy.tiling_index[0] = 28; in si_set_optimal_micro_tile_mode()
307 rtex->surface.u.legacy.tiling_index[0] = 10; in si_set_optimal_micro_tile_mode()
310 rtex->surface.u.legacy.tiling_index[0] = 11; in si_set_optimal_micro_tile_mode()
313 rtex->surface.u.legacy.tiling_index[0] = 12; in si_set_optimal_micro_tile_mode()
320 rtex->surface.u.legacy.tiling_index[0] = 14; in si_set_optimal_micro_tile_mode()
323 rtex->surface.u.legacy.tiling_index[0] = 15; in si_set_optimal_micro_tile_mode()
326 rtex->surface.u.legacy.tiling_index[0] = 16; in si_set_optimal_micro_tile_mode()
329 rtex->surface.u.legacy.tiling_index[0] = 17; in si_set_optimal_micro_tile_mode()
399 tex->surface.u.legacy.level[0].mode == RADEON_SURF_MODE_1D && in si_do_fast_color_clear()
444 !tex->surface.u.legacy.level[level].dcc_fast_clear_size) in si_do_fast_color_clear()