Lines Matching refs:sctx
39 si_init_external_atom(struct si_context *sctx, struct r600_atom *atom, in si_init_external_atom() argument
42 atom->id = list_elem - sctx->atoms.array; in si_init_external_atom()
47 void si_init_atom(struct si_context *sctx, struct r600_atom *atom, in si_init_atom() argument
52 atom->id = list_elem - sctx->atoms.array; in si_init_atom()
87 static void si_emit_cb_render_state(struct si_context *sctx, struct r600_atom *atom) in si_emit_cb_render_state() argument
89 struct radeon_winsys_cs *cs = sctx->b.gfx.cs; in si_emit_cb_render_state()
90 struct si_state_blend *blend = sctx->queued.named.blend; in si_emit_cb_render_state()
93 uint32_t cb_target_mask = sctx->framebuffer.colorbuf_enabled_4bit; in si_emit_cb_render_state()
106 sctx->ps_shader.cso && in si_emit_cb_render_state()
107 (sctx->ps_shader.cso->info.colors_written & 0x3) != 0x3) in si_emit_cb_render_state()
115 if (sctx->screen->dfsm_allowed && in si_emit_cb_render_state()
116 sctx->last_cb_target_mask != cb_target_mask) { in si_emit_cb_render_state()
117 sctx->last_cb_target_mask = cb_target_mask; in si_emit_cb_render_state()
123 if (sctx->b.chip_class >= VI) { in si_emit_cb_render_state()
128 bool oc_disable = (sctx->b.chip_class == VI || in si_emit_cb_render_state()
129 sctx->b.chip_class == GFX9) && in si_emit_cb_render_state()
132 sctx->framebuffer.nr_samples >= 2; in si_emit_cb_render_state()
141 if (sctx->screen->rbplus_allowed) { in si_emit_cb_render_state()
143 sctx->ps_shader.cso ? in si_emit_cb_render_state()
144 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format : 0; in si_emit_cb_render_state()
149 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) { in si_emit_cb_render_state()
151 (struct r600_surface*)sctx->framebuffer.state.cbufs[i]; in si_emit_cb_render_state()
269 } else if (sctx->screen->has_rbplus) { in si_emit_cb_render_state()
470 struct si_context *sctx = (struct si_context*)ctx; in si_create_blend_state_mode() local
552 si_blend_check_commutativity(sctx->screen, blend, in si_create_blend_state_mode()
554 si_blend_check_commutativity(sctx->screen, blend, in si_create_blend_state_mode()
632 if (sctx->screen->has_rbplus) { in si_create_blend_state_mode()
666 struct si_context *sctx = (struct si_context *)ctx; in si_bind_blend_state() local
667 struct si_state_blend *old_blend = sctx->queued.named.blend; in si_bind_blend_state()
673 si_pm4_bind_state(sctx, blend, state); in si_bind_blend_state()
679 sctx->framebuffer.nr_samples >= 2 && in si_bind_blend_state()
680 sctx->screen->dcc_msaa_allowed)) in si_bind_blend_state()
681 si_mark_atom_dirty(sctx, &sctx->cb_render_state); in si_bind_blend_state()
690 sctx->do_update_shaders = true; in si_bind_blend_state()
692 if (sctx->screen->dpbb_allowed && in si_bind_blend_state()
697 si_mark_atom_dirty(sctx, &sctx->dpbb_state); in si_bind_blend_state()
699 if (sctx->screen->has_out_of_order_rast && in si_bind_blend_state()
705 si_mark_atom_dirty(sctx, &sctx->msaa_config); in si_bind_blend_state()
710 struct si_context *sctx = (struct si_context *)ctx; in si_delete_blend_state() local
711 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state); in si_delete_blend_state()
717 struct si_context *sctx = (struct si_context *)ctx; in si_set_blend_color() local
720 sctx->blend_color.state = *state; in si_set_blend_color()
721 sctx->blend_color.any_nonzeros = memcmp(state, &zeros, sizeof(*state)) != 0; in si_set_blend_color()
722 si_mark_atom_dirty(sctx, &sctx->blend_color.atom); in si_set_blend_color()
725 static void si_emit_blend_color(struct si_context *sctx, struct r600_atom *atom) in si_emit_blend_color() argument
727 struct radeon_winsys_cs *cs = sctx->b.gfx.cs; in si_emit_blend_color()
730 radeon_emit_array(cs, (uint32_t*)sctx->blend_color.state.color, 4); in si_emit_blend_color()
740 struct si_context *sctx = (struct si_context *)ctx; in si_set_clip_state() local
744 if (memcmp(&sctx->clip_state.state, state, sizeof(*state)) == 0) in si_set_clip_state()
747 sctx->clip_state.state = *state; in si_set_clip_state()
748 sctx->clip_state.any_nonzeros = memcmp(state, &zeros, sizeof(*state)) != 0; in si_set_clip_state()
749 si_mark_atom_dirty(sctx, &sctx->clip_state.atom); in si_set_clip_state()
755 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES, &cb); in si_set_clip_state()
759 static void si_emit_clip_state(struct si_context *sctx, struct r600_atom *atom) in si_emit_clip_state() argument
761 struct radeon_winsys_cs *cs = sctx->b.gfx.cs; in si_emit_clip_state()
764 radeon_emit_array(cs, (uint32_t*)sctx->clip_state.state.ucp, 6*4); in si_emit_clip_state()
767 static void si_emit_clip_regs(struct si_context *sctx, struct r600_atom *atom) in si_emit_clip_regs() argument
769 struct radeon_winsys_cs *cs = sctx->b.gfx.cs; in si_emit_clip_regs()
770 struct si_shader *vs = si_get_vs_state(sctx); in si_emit_clip_regs()
773 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer; in si_emit_clip_regs()
811 static void si_update_poly_offset_state(struct si_context *sctx) in si_update_poly_offset_state() argument
813 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer; in si_update_poly_offset_state()
815 if (!rs || !rs->uses_poly_offset || !sctx->framebuffer.state.zsbuf) { in si_update_poly_offset_state()
816 si_pm4_bind_state(sctx, poly_offset, NULL); in si_update_poly_offset_state()
823 switch (sctx->framebuffer.state.zsbuf->texture->format) { in si_update_poly_offset_state()
825 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[0]); in si_update_poly_offset_state()
828 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[1]); in si_update_poly_offset_state()
832 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[2]); in si_update_poly_offset_state()
1006 struct si_context *sctx = (struct si_context *)ctx; in si_bind_rs_state() local
1008 (struct si_state_rasterizer*)sctx->queued.named.rasterizer; in si_bind_rs_state()
1015 si_mark_atom_dirty(sctx, &sctx->db_render_state); in si_bind_rs_state()
1018 if (sctx->screen->has_msaa_sample_loc_bug && in si_bind_rs_state()
1019 sctx->framebuffer.nr_samples > 1) in si_bind_rs_state()
1020 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom); in si_bind_rs_state()
1023 sctx->current_vs_state &= C_VS_STATE_CLAMP_VERTEX_COLOR; in si_bind_rs_state()
1024 sctx->current_vs_state |= S_VS_STATE_CLAMP_VERTEX_COLOR(rs->clamp_vertex_color); in si_bind_rs_state()
1026 si_pm4_bind_state(sctx, rasterizer, rs); in si_bind_rs_state()
1027 si_update_poly_offset_state(sctx); in si_bind_rs_state()
1033 sctx->scissors.dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1; in si_bind_rs_state()
1034 si_mark_atom_dirty(sctx, &sctx->scissors.atom); in si_bind_rs_state()
1039 sctx->viewports.depth_range_dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1; in si_bind_rs_state()
1040 si_mark_atom_dirty(sctx, &sctx->viewports.atom); in si_bind_rs_state()
1046 si_mark_atom_dirty(sctx, &sctx->clip_regs); in si_bind_rs_state()
1048 sctx->ia_multi_vgt_param_key.u.line_stipple_enabled = in si_bind_rs_state()
1063 sctx->do_update_shaders = true; in si_bind_rs_state()
1068 struct si_context *sctx = (struct si_context *)ctx; in si_delete_rs_state() local
1071 if (sctx->queued.named.rasterizer == state) in si_delete_rs_state()
1072 si_pm4_bind_state(sctx, poly_offset, NULL); in si_delete_rs_state()
1075 si_pm4_delete_state(sctx, rasterizer, rs); in si_delete_rs_state()
1081 static void si_emit_stencil_ref(struct si_context *sctx, struct r600_atom *atom) in si_emit_stencil_ref() argument
1083 struct radeon_winsys_cs *cs = sctx->b.gfx.cs; in si_emit_stencil_ref()
1084 struct pipe_stencil_ref *ref = &sctx->stencil_ref.state; in si_emit_stencil_ref()
1085 struct si_dsa_stencil_ref_part *dsa = &sctx->stencil_ref.dsa_part; in si_emit_stencil_ref()
1101 struct si_context *sctx = (struct si_context *)ctx; in si_set_stencil_ref() local
1103 if (memcmp(&sctx->stencil_ref.state, state, sizeof(*state)) == 0) in si_set_stencil_ref()
1106 sctx->stencil_ref.state = *state; in si_set_stencil_ref()
1107 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom); in si_set_stencil_ref()
1177 struct si_context *sctx = (struct si_context *)ctx; in si_create_dsa_state() local
1271 sctx->screen->assume_no_z_fights && in si_create_dsa_state()
1275 sctx->screen->assume_no_z_fights && in si_create_dsa_state()
1283 struct si_context *sctx = (struct si_context *)ctx; in si_bind_dsa_state() local
1284 struct si_state_dsa *old_dsa = sctx->queued.named.dsa; in si_bind_dsa_state()
1290 si_pm4_bind_state(sctx, dsa, dsa); in si_bind_dsa_state()
1292 if (memcmp(&dsa->stencil_ref, &sctx->stencil_ref.dsa_part, in si_bind_dsa_state()
1294 sctx->stencil_ref.dsa_part = dsa->stencil_ref; in si_bind_dsa_state()
1295 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom); in si_bind_dsa_state()
1299 sctx->do_update_shaders = true; in si_bind_dsa_state()
1301 if (sctx->screen->dpbb_allowed && in si_bind_dsa_state()
1306 si_mark_atom_dirty(sctx, &sctx->dpbb_state); in si_bind_dsa_state()
1308 if (sctx->screen->has_out_of_order_rast && in si_bind_dsa_state()
1312 si_mark_atom_dirty(sctx, &sctx->msaa_config); in si_bind_dsa_state()
1317 struct si_context *sctx = (struct si_context *)ctx; in si_delete_dsa_state() local
1318 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state); in si_delete_dsa_state()
1321 static void *si_create_db_flush_dsa(struct si_context *sctx) in si_create_db_flush_dsa() argument
1325 return sctx->b.b.create_depth_stencil_alpha_state(&sctx->b.b, &dsa); in si_create_db_flush_dsa()
1332 struct si_context *sctx = (struct si_context*)ctx; in si_set_active_query_state() local
1336 sctx->b.flags &= ~SI_CONTEXT_STOP_PIPELINE_STATS; in si_set_active_query_state()
1337 sctx->b.flags |= SI_CONTEXT_START_PIPELINE_STATS; in si_set_active_query_state()
1339 sctx->b.flags &= ~SI_CONTEXT_START_PIPELINE_STATS; in si_set_active_query_state()
1340 sctx->b.flags |= SI_CONTEXT_STOP_PIPELINE_STATS; in si_set_active_query_state()
1344 if (sctx->occlusion_queries_disabled != !enable) { in si_set_active_query_state()
1345 sctx->occlusion_queries_disabled = !enable; in si_set_active_query_state()
1346 si_mark_atom_dirty(sctx, &sctx->db_render_state); in si_set_active_query_state()
1354 struct si_context *sctx = (struct si_context*)ctx; in si_set_occlusion_query_state() local
1356 si_mark_atom_dirty(sctx, &sctx->db_render_state); in si_set_occlusion_query_state()
1358 bool perfect_enable = sctx->b.num_perfect_occlusion_queries != 0; in si_set_occlusion_query_state()
1361 si_mark_atom_dirty(sctx, &sctx->msaa_config); in si_set_occlusion_query_state()
1366 struct si_context *sctx = (struct si_context*)ctx; in si_save_qbo_state() local
1368 st->saved_compute = sctx->cs_shader_state.program; in si_save_qbo_state()
1370 si_get_pipe_constant_buffer(sctx, PIPE_SHADER_COMPUTE, 0, &st->saved_const0); in si_save_qbo_state()
1371 si_get_shader_buffers(sctx, PIPE_SHADER_COMPUTE, 0, 3, st->saved_ssbo); in si_save_qbo_state()
1374 static void si_emit_db_render_state(struct si_context *sctx, struct r600_atom *state) in si_emit_db_render_state() argument
1376 struct radeon_winsys_cs *cs = sctx->b.gfx.cs; in si_emit_db_render_state()
1377 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer; in si_emit_db_render_state()
1383 if (sctx->dbcb_depth_copy_enabled || in si_emit_db_render_state()
1384 sctx->dbcb_stencil_copy_enabled) { in si_emit_db_render_state()
1386 S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) | in si_emit_db_render_state()
1387 S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) | in si_emit_db_render_state()
1389 S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample)); in si_emit_db_render_state()
1390 } else if (sctx->db_flush_depth_inplace || sctx->db_flush_stencil_inplace) { in si_emit_db_render_state()
1392 S_028000_DEPTH_COMPRESS_DISABLE(sctx->db_flush_depth_inplace) | in si_emit_db_render_state()
1393 S_028000_STENCIL_COMPRESS_DISABLE(sctx->db_flush_stencil_inplace)); in si_emit_db_render_state()
1396 S_028000_DEPTH_CLEAR_ENABLE(sctx->db_depth_clear) | in si_emit_db_render_state()
1397 S_028000_STENCIL_CLEAR_ENABLE(sctx->db_stencil_clear)); in si_emit_db_render_state()
1401 if (sctx->b.num_occlusion_queries > 0 && in si_emit_db_render_state()
1402 !sctx->occlusion_queries_disabled) { in si_emit_db_render_state()
1403 bool perfect = sctx->b.num_perfect_occlusion_queries > 0; in si_emit_db_render_state()
1405 if (sctx->b.chip_class >= CIK) { in si_emit_db_render_state()
1408 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples) | in si_emit_db_render_state()
1415 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples)); in si_emit_db_render_state()
1419 if (sctx->b.chip_class >= CIK) { in si_emit_db_render_state()
1428 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx->db_depth_disable_expclear) | in si_emit_db_render_state()
1429 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx->db_stencil_disable_expclear) | in si_emit_db_render_state()
1430 S_028010_DECOMPRESS_Z_ON_FLUSH(sctx->framebuffer.nr_samples >= 4)); in si_emit_db_render_state()
1432 db_shader_control = sctx->ps_db_shader_control; in si_emit_db_render_state()
1435 if (sctx->b.chip_class == SI && sctx->smoothing_enabled) { in si_emit_db_render_state()
1444 if (sctx->screen->has_rbplus && in si_emit_db_render_state()
1445 !sctx->screen->rbplus_allowed) in si_emit_db_render_state()
2346 static void si_initialize_color_surface(struct si_context *sctx, in si_initialize_color_surface() argument
2445 if (sctx->b.chip_class == SI) { in si_initialize_color_surface()
2452 if (sctx->b.chip_class >= VI) { in si_initialize_color_surface()
2460 if (!sctx->screen->info.has_dedicated_vram) in si_initialize_color_surface()
2476 if (!rtex->fmask.size && sctx->b.chip_class == SI) { in si_initialize_color_surface()
2484 if (sctx->b.chip_class >= GFX9) { in si_initialize_color_surface()
2505 static void si_init_depth_surface(struct si_context *sctx, in si_init_depth_surface() argument
2526 if (sctx->b.chip_class >= GFX9) { in si_init_depth_surface()
2591 if (sctx->b.chip_class >= CIK) { in si_init_depth_surface()
2592 struct radeon_info *info = &sctx->screen->info; in si_init_depth_surface()
2670 void si_update_fb_dirtiness_after_rendering(struct si_context *sctx) in si_update_fb_dirtiness_after_rendering() argument
2672 if (sctx->decompression_enabled) in si_update_fb_dirtiness_after_rendering()
2675 if (sctx->framebuffer.state.zsbuf) { in si_update_fb_dirtiness_after_rendering()
2676 struct pipe_surface *surf = sctx->framebuffer.state.zsbuf; in si_update_fb_dirtiness_after_rendering()
2685 unsigned compressed_cb_mask = sctx->framebuffer.compressed_cb_mask; in si_update_fb_dirtiness_after_rendering()
2688 struct pipe_surface *surf = sctx->framebuffer.state.cbufs[i]; in si_update_fb_dirtiness_after_rendering()
2716 struct si_context *sctx = (struct si_context *)ctx; in si_set_framebuffer_state() local
2720 bool old_any_dst_linear = sctx->framebuffer.any_dst_linear; in si_set_framebuffer_state()
2721 unsigned old_nr_samples = sctx->framebuffer.nr_samples; in si_set_framebuffer_state()
2722 unsigned old_colorbuf_enabled_4bit = sctx->framebuffer.colorbuf_enabled_4bit; in si_set_framebuffer_state()
2723 bool old_has_zsbuf = !!sctx->framebuffer.state.zsbuf; in si_set_framebuffer_state()
2726 ((struct r600_texture*)sctx->framebuffer.state.zsbuf->texture)->surface.has_stencil; in si_set_framebuffer_state()
2730 si_update_fb_dirtiness_after_rendering(sctx); in si_set_framebuffer_state()
2732 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) { in si_set_framebuffer_state()
2733 if (!sctx->framebuffer.state.cbufs[i]) in si_set_framebuffer_state()
2736 rtex = (struct r600_texture*)sctx->framebuffer.state.cbufs[i]->texture; in si_set_framebuffer_state()
2758 util_copy_framebuffer_state(&sctx->framebuffer.state, NULL); in si_set_framebuffer_state()
2763 if (!si_texture_disable_dcc(&sctx->b, rtex)) in si_set_framebuffer_state()
2764 sctx->b.decompress_dcc(ctx, rtex); in si_set_framebuffer_state()
2786 if (sctx->framebuffer.nr_samples <= 1 && in si_set_framebuffer_state()
2787 sctx->framebuffer.state.nr_cbufs) in si_set_framebuffer_state()
2788 si_make_CB_shader_coherent(sctx, sctx->framebuffer.nr_samples, in si_set_framebuffer_state()
2789 sctx->framebuffer.CB_has_shader_readable_metadata); in si_set_framebuffer_state()
2791 sctx->b.flags |= SI_CONTEXT_CS_PARTIAL_FLUSH; in si_set_framebuffer_state()
2799 if (sctx->generate_mipmap_for_depth) { in si_set_framebuffer_state()
2800 si_make_DB_shader_coherent(sctx, 1, false, in si_set_framebuffer_state()
2801 sctx->framebuffer.DB_has_shader_readable_metadata); in si_set_framebuffer_state()
2802 } else if (sctx->b.chip_class == GFX9) { in si_set_framebuffer_state()
2809 sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_DB_META; in si_set_framebuffer_state()
2815 sctx->framebuffer.dirty_cbufs |= in si_set_framebuffer_state()
2816 (1 << MAX2(sctx->framebuffer.state.nr_cbufs, state->nr_cbufs)) - 1; in si_set_framebuffer_state()
2817 sctx->framebuffer.dirty_zsbuf |= sctx->framebuffer.state.zsbuf != state->zsbuf; in si_set_framebuffer_state()
2819 si_dec_framebuffer_counters(&sctx->framebuffer.state); in si_set_framebuffer_state()
2820 util_copy_framebuffer_state(&sctx->framebuffer.state, state); in si_set_framebuffer_state()
2822 sctx->framebuffer.colorbuf_enabled_4bit = 0; in si_set_framebuffer_state()
2823 sctx->framebuffer.spi_shader_col_format = 0; in si_set_framebuffer_state()
2824 sctx->framebuffer.spi_shader_col_format_alpha = 0; in si_set_framebuffer_state()
2825 sctx->framebuffer.spi_shader_col_format_blend = 0; in si_set_framebuffer_state()
2826 sctx->framebuffer.spi_shader_col_format_blend_alpha = 0; in si_set_framebuffer_state()
2827 sctx->framebuffer.color_is_int8 = 0; in si_set_framebuffer_state()
2828 sctx->framebuffer.color_is_int10 = 0; in si_set_framebuffer_state()
2830 sctx->framebuffer.compressed_cb_mask = 0; in si_set_framebuffer_state()
2831 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state); in si_set_framebuffer_state()
2832 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples); in si_set_framebuffer_state()
2833 sctx->framebuffer.any_dst_linear = false; in si_set_framebuffer_state()
2834 sctx->framebuffer.CB_has_shader_readable_metadata = false; in si_set_framebuffer_state()
2835 sctx->framebuffer.DB_has_shader_readable_metadata = false; in si_set_framebuffer_state()
2845 si_initialize_color_surface(sctx, surf); in si_set_framebuffer_state()
2848 sctx->framebuffer.colorbuf_enabled_4bit |= 0xf << (i * 4); in si_set_framebuffer_state()
2849 sctx->framebuffer.spi_shader_col_format |= in si_set_framebuffer_state()
2851 sctx->framebuffer.spi_shader_col_format_alpha |= in si_set_framebuffer_state()
2853 sctx->framebuffer.spi_shader_col_format_blend |= in si_set_framebuffer_state()
2855 sctx->framebuffer.spi_shader_col_format_blend_alpha |= in si_set_framebuffer_state()
2859 sctx->framebuffer.color_is_int8 |= 1 << i; in si_set_framebuffer_state()
2861 sctx->framebuffer.color_is_int10 |= 1 << i; in si_set_framebuffer_state()
2864 sctx->framebuffer.compressed_cb_mask |= 1 << i; in si_set_framebuffer_state()
2868 sctx->framebuffer.any_dst_linear = true; in si_set_framebuffer_state()
2871 sctx->framebuffer.CB_has_shader_readable_metadata = true; in si_set_framebuffer_state()
2879 sctx->framebuffer.compressed_cb_mask |= 1 << i; in si_set_framebuffer_state()
2891 si_init_depth_surface(sctx, surf); in si_set_framebuffer_state()
2895 sctx->framebuffer.DB_has_shader_readable_metadata = true; in si_set_framebuffer_state()
2900 si_update_poly_offset_state(sctx); in si_set_framebuffer_state()
2901 si_mark_atom_dirty(sctx, &sctx->cb_render_state); in si_set_framebuffer_state()
2902 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom); in si_set_framebuffer_state()
2904 if (sctx->screen->dpbb_allowed) in si_set_framebuffer_state()
2905 si_mark_atom_dirty(sctx, &sctx->dpbb_state); in si_set_framebuffer_state()
2907 if (sctx->framebuffer.any_dst_linear != old_any_dst_linear) in si_set_framebuffer_state()
2908 si_mark_atom_dirty(sctx, &sctx->msaa_config); in si_set_framebuffer_state()
2910 if (sctx->screen->has_out_of_order_rast && in si_set_framebuffer_state()
2911 (sctx->framebuffer.colorbuf_enabled_4bit != old_colorbuf_enabled_4bit || in si_set_framebuffer_state()
2912 !!sctx->framebuffer.state.zsbuf != old_has_zsbuf || in si_set_framebuffer_state()
2914 si_mark_atom_dirty(sctx, &sctx->msaa_config); in si_set_framebuffer_state()
2916 if (sctx->framebuffer.nr_samples != old_nr_samples) { in si_set_framebuffer_state()
2917 si_mark_atom_dirty(sctx, &sctx->msaa_config); in si_set_framebuffer_state()
2918 si_mark_atom_dirty(sctx, &sctx->db_render_state); in si_set_framebuffer_state()
2921 switch (sctx->framebuffer.nr_samples) { in si_set_framebuffer_state()
2923 constbuf.user_buffer = sctx->sample_locations_1x; in si_set_framebuffer_state()
2926 constbuf.user_buffer = sctx->sample_locations_2x; in si_set_framebuffer_state()
2929 constbuf.user_buffer = sctx->sample_locations_4x; in si_set_framebuffer_state()
2932 constbuf.user_buffer = sctx->sample_locations_8x; in si_set_framebuffer_state()
2935 constbuf.user_buffer = sctx->sample_locations_16x; in si_set_framebuffer_state()
2939 sctx->framebuffer.nr_samples); in si_set_framebuffer_state()
2942 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4; in si_set_framebuffer_state()
2943 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS, &constbuf); in si_set_framebuffer_state()
2945 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom); in si_set_framebuffer_state()
2948 sctx->do_update_shaders = true; in si_set_framebuffer_state()
2950 if (!sctx->decompression_enabled) { in si_set_framebuffer_state()
2954 sctx->need_check_render_feedback = true; in si_set_framebuffer_state()
2958 static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom *atom) in si_emit_framebuffer_state() argument
2960 struct radeon_winsys_cs *cs = sctx->b.gfx.cs; in si_emit_framebuffer_state()
2961 struct pipe_framebuffer_state *state = &sctx->framebuffer.state; in si_emit_framebuffer_state()
2972 if (!(sctx->framebuffer.dirty_cbufs & (1 << i))) in si_emit_framebuffer_state()
2983 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, in si_emit_framebuffer_state()
2990 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, in si_emit_framebuffer_state()
2996 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, in si_emit_framebuffer_state()
3028 if (sctx->b.chip_class >= GFX9) { in si_emit_framebuffer_state()
3092 if (sctx->b.chip_class >= CIK) in si_emit_framebuffer_state()
3098 if (sctx->b.chip_class >= CIK) in si_emit_framebuffer_state()
3105 sctx->b.chip_class >= VI ? 14 : 13); in si_emit_framebuffer_state()
3120 if (sctx->b.chip_class >= VI) /* R_028C94_CB_COLOR0_DCC_BASE */ in si_emit_framebuffer_state()
3125 if (sctx->framebuffer.dirty_cbufs & (1 << i)) in si_emit_framebuffer_state()
3129 if (state->zsbuf && sctx->framebuffer.dirty_zsbuf) { in si_emit_framebuffer_state()
3133 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, in si_emit_framebuffer_state()
3139 if (sctx->b.chip_class >= GFX9) { in si_emit_framebuffer_state()
3183 } else if (sctx->framebuffer.dirty_zsbuf) { in si_emit_framebuffer_state()
3184 if (sctx->b.chip_class >= GFX9) in si_emit_framebuffer_state()
3198 if (sctx->screen->dfsm_allowed) { in si_emit_framebuffer_state()
3203 sctx->framebuffer.dirty_cbufs = 0; in si_emit_framebuffer_state()
3204 sctx->framebuffer.dirty_zsbuf = false; in si_emit_framebuffer_state()
3207 static void si_emit_msaa_sample_locs(struct si_context *sctx, in si_emit_msaa_sample_locs() argument
3210 struct radeon_winsys_cs *cs = sctx->b.gfx.cs; in si_emit_msaa_sample_locs()
3211 unsigned nr_samples = sctx->framebuffer.nr_samples; in si_emit_msaa_sample_locs()
3212 bool has_msaa_sample_loc_bug = sctx->screen->has_msaa_sample_loc_bug; in si_emit_msaa_sample_locs()
3217 if (nr_samples <= 1 && sctx->smoothing_enabled) in si_emit_msaa_sample_locs()
3226 if (nr_samples != sctx->msaa_sample_locs.nr_samples) { in si_emit_msaa_sample_locs()
3227 sctx->msaa_sample_locs.nr_samples = nr_samples; in si_emit_msaa_sample_locs()
3231 if (sctx->b.family >= CHIP_POLARIS10) { in si_emit_msaa_sample_locs()
3232 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer; in si_emit_msaa_sample_locs()
3236 S_028830_LINE_FILTER_DISABLE(sctx->b.family <= CHIP_POLARIS12); in si_emit_msaa_sample_locs()
3243 sctx->framebuffer.nr_samples > 1 && in si_emit_msaa_sample_locs()
3252 static bool si_out_of_order_rasterization(struct si_context *sctx) in si_out_of_order_rasterization() argument
3254 struct si_state_blend *blend = sctx->queued.named.blend; in si_out_of_order_rasterization()
3255 struct si_state_dsa *dsa = sctx->queued.named.dsa; in si_out_of_order_rasterization()
3257 if (!sctx->screen->has_out_of_order_rast) in si_out_of_order_rasterization()
3260 unsigned colormask = sctx->framebuffer.colorbuf_enabled_4bit; in si_out_of_order_rasterization()
3276 if (sctx->framebuffer.state.zsbuf) { in si_out_of_order_rasterization()
3278 (struct r600_texture*)sctx->framebuffer.state.zsbuf->texture; in si_out_of_order_rasterization()
3286 if (sctx->ps_shader.cso && in si_out_of_order_rasterization()
3287 sctx->ps_shader.cso->info.writes_memory && in si_out_of_order_rasterization()
3288 sctx->ps_shader.cso->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] && in si_out_of_order_rasterization()
3292 if (sctx->b.num_perfect_occlusion_queries != 0 && in si_out_of_order_rasterization()
3319 static void si_emit_msaa_config(struct si_context *sctx, struct r600_atom *atom) in si_emit_msaa_config() argument
3321 struct radeon_winsys_cs *cs = sctx->b.gfx.cs; in si_emit_msaa_config()
3322 unsigned num_tile_pipes = sctx->screen->info.num_tile_pipes; in si_emit_msaa_config()
3324 bool dst_is_linear = sctx->framebuffer.any_dst_linear; in si_emit_msaa_config()
3325 bool out_of_order_rast = si_out_of_order_rasterization(sctx); in si_emit_msaa_config()
3340 int setup_samples = sctx->framebuffer.nr_samples > 1 ? sctx->framebuffer.nr_samples : in si_emit_msaa_config()
3341 sctx->smoothing_enabled ? SI_NUM_SMOOTH_AA_SAMPLES : 0; in si_emit_msaa_config()
3363 util_logbase2(util_next_power_of_two(sctx->ps_iter_samples)); in si_emit_msaa_config()
3372 if (sctx->framebuffer.nr_samples > 1) { in si_emit_msaa_config()
3381 S_028A4C_PS_ITER_SAMPLE(sctx->ps_iter_samples > 1) | in si_emit_msaa_config()
3383 } else if (sctx->smoothing_enabled) { in si_emit_msaa_config()
3404 if (sctx->screen->dfsm_allowed) { in si_emit_msaa_config()
3412 struct si_context *sctx = (struct si_context *)ctx; in si_set_min_samples() local
3414 if (sctx->ps_iter_samples == min_samples) in si_set_min_samples()
3417 sctx->ps_iter_samples = min_samples; in si_set_min_samples()
3418 sctx->do_update_shaders = true; in si_set_min_samples()
3420 if (sctx->framebuffer.nr_samples > 1) in si_set_min_samples()
3421 si_mark_atom_dirty(sctx, &sctx->msaa_config); in si_set_min_samples()
3422 if (sctx->screen->dpbb_allowed) in si_set_min_samples()
3423 si_mark_atom_dirty(sctx, &sctx->dpbb_state); in si_set_min_samples()
3832 struct si_context *sctx = (struct si_context*)ctx; in si_create_sampler_view_custom() local
3862 si_make_buffer_descriptor(sctx->screen, in si_create_sampler_view_custom()
3883 if (sctx->b.chip_class <= VI && force_level) { in si_create_sampler_view_custom()
3956 si_make_texture_descriptor(sctx->screen, tmp, true, in si_create_sampler_view_custom()
4003 static uint32_t si_translate_border_color(struct si_context *sctx, in si_translate_border_color() argument
4039 for (i = 0; i < sctx->border_color_count; i++) in si_translate_border_color()
4040 if (memcmp(&sctx->border_color_table[i], color, in si_translate_border_color()
4052 if (i == sctx->border_color_count) { in si_translate_border_color()
4054 memcpy(&sctx->border_color_table[i], color, in si_translate_border_color()
4056 util_memcpy_cpu_to_le32(&sctx->border_color_map[i], in si_translate_border_color()
4058 sctx->border_color_count++; in si_translate_border_color()
4096 struct si_context *sctx = (struct si_context *)ctx; in si_create_sampler_state() local
4097 struct si_screen *sscreen = sctx->screen; in si_create_sampler_state()
4120 S_008F30_COMPAT_MODE(sctx->b.chip_class >= VI)); in si_create_sampler_state()
4129 S_008F38_DISABLE_LSB_CEIL(sctx->b.chip_class <= VI) | in si_create_sampler_state()
4131 S_008F38_ANISO_OVERRIDE(sctx->b.chip_class >= VI)); in si_create_sampler_state()
4132 rstate->val[3] = si_translate_border_color(sctx, state, &state->border_color, false); in si_create_sampler_state()
4136 rstate->integer_val[3] = si_translate_border_color(sctx, state, &state->border_color, true); in si_create_sampler_state()
4151 si_translate_border_color(sctx, state, &clamped_border_color, false) | in si_create_sampler_state()
4159 struct si_context *sctx = (struct si_context *)ctx; in si_set_sample_mask() local
4161 if (sctx->sample_mask.sample_mask == (uint16_t)sample_mask) in si_set_sample_mask()
4164 sctx->sample_mask.sample_mask = sample_mask; in si_set_sample_mask()
4165 si_mark_atom_dirty(sctx, &sctx->sample_mask.atom); in si_set_sample_mask()
4168 static void si_emit_sample_mask(struct si_context *sctx, struct r600_atom *atom) in si_emit_sample_mask() argument
4170 struct radeon_winsys_cs *cs = sctx->b.gfx.cs; in si_emit_sample_mask()
4171 unsigned mask = sctx->sample_mask.sample_mask; in si_emit_sample_mask()
4177 assert(mask == 0xffff || sctx->framebuffer.nr_samples > 1 || in si_emit_sample_mask()
4178 (mask & 1 && sctx->blitter->running)); in si_emit_sample_mask()
4351 struct si_context *sctx = (struct si_context *)ctx; in si_bind_vertex_elements() local
4352 struct si_vertex_elements *old = sctx->vertex_elements; in si_bind_vertex_elements()
4355 sctx->vertex_elements = v; in si_bind_vertex_elements()
4356 sctx->vertex_buffers_dirty = true; in si_bind_vertex_elements()
4364 sctx->do_update_shaders = true; in si_bind_vertex_elements()
4373 si_set_rw_buffer(sctx, SI_VS_CONST_INSTANCE_DIVISORS, &cb); in si_bind_vertex_elements()
4379 struct si_context *sctx = (struct si_context *)ctx; in si_delete_vertex_element() local
4381 if (sctx->vertex_elements == state) in si_delete_vertex_element()
4382 sctx->vertex_elements = NULL; in si_delete_vertex_element()
4390 struct si_context *sctx = (struct si_context *)ctx; in si_set_vertex_buffers() local
4391 struct pipe_vertex_buffer *dst = sctx->vertex_buffer + start_slot; in si_set_vertex_buffers()
4394 assert(start_slot + count <= ARRAY_SIZE(sctx->vertex_buffer)); in si_set_vertex_buffers()
4414 sctx->vertex_buffers_dirty = true; in si_set_vertex_buffers()
4425 struct si_context *sctx = (struct si_context *)ctx; in si_set_tess_state() local
4436 si_upload_const_buffer(sctx, (struct r600_resource**)&cb.buffer, in si_set_tess_state()
4440 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS, &cb); in si_set_tess_state()
4446 struct si_context *sctx = (struct si_context *)ctx; in si_texture_barrier() local
4448 si_update_fb_dirtiness_after_rendering(sctx); in si_texture_barrier()
4451 if (sctx->framebuffer.nr_samples <= 1 && in si_texture_barrier()
4452 sctx->framebuffer.state.nr_cbufs) in si_texture_barrier()
4453 si_make_CB_shader_coherent(sctx, sctx->framebuffer.nr_samples, in si_texture_barrier()
4454 sctx->framebuffer.CB_has_shader_readable_metadata); in si_texture_barrier()
4460 struct si_context *sctx = (struct si_context *)ctx; in si_memory_barrier() local
4464 sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH | in si_memory_barrier()
4468 sctx->b.flags |= SI_CONTEXT_INV_SMEM_L1 | in si_memory_barrier()
4480 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1; in si_memory_barrier()
4487 if (sctx->screen->info.chip_class <= CIK) in si_memory_barrier()
4488 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2; in si_memory_barrier()
4495 sctx->framebuffer.nr_samples <= 1 && in si_memory_barrier()
4496 sctx->framebuffer.state.nr_cbufs) { in si_memory_barrier()
4497 sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_CB; in si_memory_barrier()
4499 if (sctx->b.chip_class <= VI) in si_memory_barrier()
4500 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2; in si_memory_barrier()
4504 if (sctx->screen->info.chip_class <= VI && in si_memory_barrier()
4506 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2; in si_memory_barrier()
4509 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode) in si_create_blend_custom() argument
4516 return si_create_blend_state_mode(&sctx->b.b, &blend, mode); in si_create_blend_custom()
4525 static void si_init_config(struct si_context *sctx);
4527 void si_init_state_functions(struct si_context *sctx) in si_init_state_functions() argument
4529 si_init_external_atom(sctx, &sctx->b.render_cond_atom, &sctx->atoms.s.render_cond); in si_init_state_functions()
4530 si_init_external_atom(sctx, &sctx->streamout.begin_atom, &sctx->atoms.s.streamout_begin); in si_init_state_functions()
4531 si_init_external_atom(sctx, &sctx->streamout.enable_atom, &sctx->atoms.s.streamout_enable); in si_init_state_functions()
4532 si_init_external_atom(sctx, &sctx->scissors.atom, &sctx->atoms.s.scissors); in si_init_state_functions()
4533 si_init_external_atom(sctx, &sctx->viewports.atom, &sctx->atoms.s.viewports); in si_init_state_functions()
4535 si_init_atom(sctx, &sctx->framebuffer.atom, &sctx->atoms.s.framebuffer, si_emit_framebuffer_state); in si_init_state_functions()
4536 …si_init_atom(sctx, &sctx->msaa_sample_locs.atom, &sctx->atoms.s.msaa_sample_locs, si_emit_msaa_sam… in si_init_state_functions()
4537 …si_init_atom(sctx, &sctx->db_render_state, &sctx->atoms.s.db_render_state, si_emit_db_render_state… in si_init_state_functions()
4538 si_init_atom(sctx, &sctx->dpbb_state, &sctx->atoms.s.dpbb_state, si_emit_dpbb_state); in si_init_state_functions()
4539 si_init_atom(sctx, &sctx->msaa_config, &sctx->atoms.s.msaa_config, si_emit_msaa_config); in si_init_state_functions()
4540 si_init_atom(sctx, &sctx->sample_mask.atom, &sctx->atoms.s.sample_mask, si_emit_sample_mask); in si_init_state_functions()
4541 …si_init_atom(sctx, &sctx->cb_render_state, &sctx->atoms.s.cb_render_state, si_emit_cb_render_state… in si_init_state_functions()
4542 si_init_atom(sctx, &sctx->blend_color.atom, &sctx->atoms.s.blend_color, si_emit_blend_color); in si_init_state_functions()
4543 si_init_atom(sctx, &sctx->clip_regs, &sctx->atoms.s.clip_regs, si_emit_clip_regs); in si_init_state_functions()
4544 si_init_atom(sctx, &sctx->clip_state.atom, &sctx->atoms.s.clip_state, si_emit_clip_state); in si_init_state_functions()
4545 si_init_atom(sctx, &sctx->stencil_ref.atom, &sctx->atoms.s.stencil_ref, si_emit_stencil_ref); in si_init_state_functions()
4547 sctx->b.b.create_blend_state = si_create_blend_state; in si_init_state_functions()
4548 sctx->b.b.bind_blend_state = si_bind_blend_state; in si_init_state_functions()
4549 sctx->b.b.delete_blend_state = si_delete_blend_state; in si_init_state_functions()
4550 sctx->b.b.set_blend_color = si_set_blend_color; in si_init_state_functions()
4552 sctx->b.b.create_rasterizer_state = si_create_rs_state; in si_init_state_functions()
4553 sctx->b.b.bind_rasterizer_state = si_bind_rs_state; in si_init_state_functions()
4554 sctx->b.b.delete_rasterizer_state = si_delete_rs_state; in si_init_state_functions()
4556 sctx->b.b.create_depth_stencil_alpha_state = si_create_dsa_state; in si_init_state_functions()
4557 sctx->b.b.bind_depth_stencil_alpha_state = si_bind_dsa_state; in si_init_state_functions()
4558 sctx->b.b.delete_depth_stencil_alpha_state = si_delete_dsa_state; in si_init_state_functions()
4560 sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx); in si_init_state_functions()
4561 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE); in si_init_state_functions()
4562 sctx->custom_blend_fmask_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS); in si_init_state_functions()
4563 …sctx->custom_blend_eliminate_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_C… in si_init_state_functions()
4564 sctx->custom_blend_dcc_decompress = si_create_blend_custom(sctx, V_028808_CB_DCC_DECOMPRESS); in si_init_state_functions()
4566 sctx->b.b.set_clip_state = si_set_clip_state; in si_init_state_functions()
4567 sctx->b.b.set_stencil_ref = si_set_stencil_ref; in si_init_state_functions()
4569 sctx->b.b.set_framebuffer_state = si_set_framebuffer_state; in si_init_state_functions()
4571 sctx->b.b.create_sampler_state = si_create_sampler_state; in si_init_state_functions()
4572 sctx->b.b.delete_sampler_state = si_delete_sampler_state; in si_init_state_functions()
4574 sctx->b.b.create_sampler_view = si_create_sampler_view; in si_init_state_functions()
4575 sctx->b.b.sampler_view_destroy = si_sampler_view_destroy; in si_init_state_functions()
4577 sctx->b.b.set_sample_mask = si_set_sample_mask; in si_init_state_functions()
4579 sctx->b.b.create_vertex_elements_state = si_create_vertex_elements; in si_init_state_functions()
4580 sctx->b.b.bind_vertex_elements_state = si_bind_vertex_elements; in si_init_state_functions()
4581 sctx->b.b.delete_vertex_elements_state = si_delete_vertex_element; in si_init_state_functions()
4582 sctx->b.b.set_vertex_buffers = si_set_vertex_buffers; in si_init_state_functions()
4584 sctx->b.b.texture_barrier = si_texture_barrier; in si_init_state_functions()
4585 sctx->b.b.memory_barrier = si_memory_barrier; in si_init_state_functions()
4586 sctx->b.b.set_min_samples = si_set_min_samples; in si_init_state_functions()
4587 sctx->b.b.set_tess_state = si_set_tess_state; in si_init_state_functions()
4589 sctx->b.b.set_active_query_state = si_set_active_query_state; in si_init_state_functions()
4590 sctx->b.set_occlusion_query_state = si_set_occlusion_query_state; in si_init_state_functions()
4591 sctx->b.save_qbo_state = si_save_qbo_state; in si_init_state_functions()
4592 sctx->b.need_gfx_cs_space = si_need_gfx_cs_space; in si_init_state_functions()
4594 sctx->b.b.draw_vbo = si_draw_vbo; in si_init_state_functions()
4596 si_init_config(sctx); in si_init_state_functions()
4604 static void si_set_grbm_gfx_index(struct si_context *sctx, in si_set_grbm_gfx_index() argument
4607 unsigned reg = sctx->b.chip_class >= CIK ? R_030800_GRBM_GFX_INDEX : in si_set_grbm_gfx_index()
4612 static void si_set_grbm_gfx_index_se(struct si_context *sctx, in si_set_grbm_gfx_index_se() argument
4615 assert(se == ~0 || se < sctx->screen->info.max_se); in si_set_grbm_gfx_index_se()
4616 si_set_grbm_gfx_index(sctx, pm4, in si_set_grbm_gfx_index_se()
4624 si_write_harvested_raster_configs(struct si_context *sctx, in si_write_harvested_raster_configs() argument
4629 unsigned sh_per_se = MAX2(sctx->screen->info.max_sh_per_se, 1); in si_write_harvested_raster_configs()
4630 unsigned num_se = MAX2(sctx->screen->info.max_se, 1); in si_write_harvested_raster_configs()
4631 unsigned rb_mask = sctx->screen->info.enabled_rb_mask; in si_write_harvested_raster_configs()
4632 unsigned num_rb = MIN2(sctx->screen->info.num_render_backends, 16); in si_write_harvested_raster_configs()
4725 si_set_grbm_gfx_index_se(sctx, pm4, se); in si_write_harvested_raster_configs()
4728 si_set_grbm_gfx_index(sctx, pm4, ~0); in si_write_harvested_raster_configs()
4730 if (sctx->b.chip_class >= CIK) { in si_write_harvested_raster_configs()
4748 static void si_set_raster_config(struct si_context *sctx, struct si_pm4_state *pm4) in si_set_raster_config() argument
4750 struct si_screen *sscreen = sctx->screen; in si_set_raster_config()
4751 unsigned num_rb = MIN2(sctx->screen->info.num_render_backends, 16); in si_set_raster_config()
4752 unsigned rb_mask = sctx->screen->info.enabled_rb_mask; in si_set_raster_config()
4755 switch (sctx->b.family) { in si_set_raster_config()
4839 if (sctx->b.chip_class >= CIK) in si_set_raster_config()
4843 si_write_harvested_raster_configs(sctx, pm4, raster_config, raster_config_1); in si_set_raster_config()
4847 static void si_init_config(struct si_context *sctx) in si_init_config() argument
4849 struct si_screen *sscreen = sctx->screen; in si_init_config()
4850 uint64_t border_color_va = sctx->border_color_buffer->gpu_address; in si_init_config()
4871 if (sctx->b.chip_class <= VI) in si_init_config()
4872 si_set_raster_config(sctx, pm4); in si_init_config()
4879 if (sctx->b.chip_class <= VI) { in si_init_config()
4893 if (sctx->b.chip_class < CIK) in si_init_config()
4906 if (sctx->b.chip_class <= CIK) { in si_init_config()
4937 if (sctx->b.chip_class >= GFX9) { in si_init_config()
4951 if (sctx->b.chip_class >= CIK) { in si_init_config()
4952 if (sctx->b.chip_class >= GFX9) { in si_init_config()
4980 if (sctx->b.family == CHIP_KABINI) { in si_init_config()
5012 if (sctx->b.chip_class >= VI) { in si_init_config()
5024 if (sctx->b.family == CHIP_FIJI || in si_init_config()
5025 sctx->b.family >= CHIP_POLARIS10) in si_init_config()
5035 if (sctx->b.chip_class >= CIK) in si_init_config()
5037 si_pm4_add_bo(pm4, sctx->border_color_buffer, RADEON_USAGE_READ, in si_init_config()
5040 if (sctx->b.chip_class >= GFX9) { in si_init_config()
5044 switch (sctx->b.family) { in si_init_config()
5063 si_pm4_upload_indirect_buffer(sctx, pm4); in si_init_config()
5064 sctx->init_config = pm4; in si_init_config()