136   IndexedMap<RegInfo, VirtReg2IndexFunctor> ExtraRegInfo;  member in __anon97cedd6b0111::RAGreedy
139     return ExtraRegInfo[VirtReg.reg].Stage;  in getStage()
143     ExtraRegInfo.resize(MRI->getNumVirtRegs());  in setStage()
144     ExtraRegInfo[VirtReg.reg].Stage = Stage;  in setStage()
149     ExtraRegInfo.resize(MRI->getNumVirtRegs());  in setStage()
152       if (ExtraRegInfo[Reg].Stage == RS_New)  in setStage()
153         ExtraRegInfo[Reg].Stage = NewStage;  in setStage()
381   if (!ExtraRegInfo.inBounds(Old))  in LRE_DidCloneVirtReg()
388   ExtraRegInfo[Old].Stage = RS_Assign;  in LRE_DidCloneVirtReg()
389   ExtraRegInfo.grow(New);  in LRE_DidCloneVirtReg()
390   ExtraRegInfo[New] = ExtraRegInfo[Old];  in LRE_DidCloneVirtReg()
395   ExtraRegInfo.clear();  in releaseMemory()
409   ExtraRegInfo.grow(Reg);  in enqueue()
410   if (ExtraRegInfo[Reg].Stage == RS_New)  in enqueue()
411     ExtraRegInfo[Reg].Stage = RS_Assign;  in enqueue()
413   if (ExtraRegInfo[Reg].Stage == RS_Split) {  in enqueue()
530   unsigned Cascade = ExtraRegInfo[VirtReg.reg].Cascade;  in canEvictInterference()
554       unsigned IntfCascade = ExtraRegInfo[Intf->reg].Cascade;  in canEvictInterference()
587   unsigned Cascade = ExtraRegInfo[VirtReg.reg].Cascade;  in evictInterference()
589     Cascade = ExtraRegInfo[VirtReg.reg].Cascade = NextCascade++;  in evictInterference()
599       assert((ExtraRegInfo[Intf->reg].Cascade < Cascade ||  in evictInterference()
602       ExtraRegInfo[Intf->reg].Cascade = Cascade;  in evictInterference()
1043   ExtraRegInfo.resize(MRI->getNumVirtRegs());  in splitAroundRegion()
1242   ExtraRegInfo.resize(MRI->getNumVirtRegs());  in tryBlockSplit()
1563                << " Cascade " << ExtraRegInfo[VirtReg.reg].Cascade << '\n');  in selectOrSplit()
1628   ExtraRegInfo.clear();  in runOnMachineFunction()
1629   ExtraRegInfo.resize(MRI->getNumVirtRegs());  in runOnMachineFunction()