Lines Matching refs:NewMIs

957         SmallVector<MachineInstr *, 2> NewMIs;  in TryInstructionTransform()  local
960 NewMIs)) { in TryInstructionTransform()
964 assert(NewMIs.size() == 2 && in TryInstructionTransform()
967 NewMIs[1]->addRegisterKilled(Reg, TRI); in TryInstructionTransform()
971 mbbi->insert(mi, NewMIs[0]); in TryInstructionTransform()
972 mbbi->insert(mi, NewMIs[1]); in TryInstructionTransform()
974 DEBUG(dbgs() << "2addr: NEW LOAD: " << *NewMIs[0] in TryInstructionTransform()
975 << "2addr: NEW INST: " << *NewMIs[1]); in TryInstructionTransform()
978 unsigned NewDstIdx = NewMIs[1]->findRegisterDefOperandIdx(regA); in TryInstructionTransform()
979 unsigned NewSrcIdx = NewMIs[1]->findRegisterUseOperandIdx(regB); in TryInstructionTransform()
980 MachineBasicBlock::iterator NewMI = NewMIs[1]; in TryInstructionTransform()
985 NewMIs[1]->getOperand(NewSrcIdx).isKill()) { in TryInstructionTransform()
995 if (NewMIs[0]->killsRegister(MO.getReg())) in TryInstructionTransform()
996 LV->replaceKillInstruction(MO.getReg(), mi, NewMIs[0]); in TryInstructionTransform()
998 assert(NewMIs[1]->killsRegister(MO.getReg()) && in TryInstructionTransform()
1000 LV->replaceKillInstruction(MO.getReg(), mi, NewMIs[1]); in TryInstructionTransform()
1004 if (NewMIs[1]->registerDefIsDead(MO.getReg())) in TryInstructionTransform()
1005 LV->addVirtualRegisterDead(MO.getReg(), NewMIs[1]); in TryInstructionTransform()
1007 assert(NewMIs[0]->registerDefIsDead(MO.getReg()) && in TryInstructionTransform()
1009 LV->addVirtualRegisterDead(MO.getReg(), NewMIs[0]); in TryInstructionTransform()
1014 LV->addVirtualRegisterKilled(Reg, NewMIs[1]); in TryInstructionTransform()
1017 mi = NewMIs[1]; in TryInstructionTransform()
1025 NewMIs[0]->eraseFromParent(); in TryInstructionTransform()
1026 NewMIs[1]->eraseFromParent(); in TryInstructionTransform()