Lines Matching refs:IValueT
33 static constexpr IValueT kWordSize = sizeof(WordType);
36 static constexpr IValueT B0 = 1;
37 static constexpr IValueT B1 = 1 << 1;
38 static constexpr IValueT B2 = 1 << 2;
39 static constexpr IValueT B3 = 1 << 3;
40 static constexpr IValueT B4 = 1 << 4;
41 static constexpr IValueT B5 = 1 << 5;
42 static constexpr IValueT B6 = 1 << 6;
43 static constexpr IValueT B7 = 1 << 7;
44 static constexpr IValueT B8 = 1 << 8;
45 static constexpr IValueT B9 = 1 << 9;
46 static constexpr IValueT B10 = 1 << 10;
47 static constexpr IValueT B11 = 1 << 11;
48 static constexpr IValueT B12 = 1 << 12;
49 static constexpr IValueT B13 = 1 << 13;
50 static constexpr IValueT B14 = 1 << 14;
51 static constexpr IValueT B15 = 1 << 15;
52 static constexpr IValueT B16 = 1 << 16;
53 static constexpr IValueT B17 = 1 << 17;
54 static constexpr IValueT B18 = 1 << 18;
55 static constexpr IValueT B19 = 1 << 19;
56 static constexpr IValueT B20 = 1 << 20;
57 static constexpr IValueT B21 = 1 << 21;
58 static constexpr IValueT B22 = 1 << 22;
59 static constexpr IValueT B23 = 1 << 23;
60 static constexpr IValueT B24 = 1 << 24;
61 static constexpr IValueT B25 = 1 << 25;
62 static constexpr IValueT B26 = 1 << 26;
63 static constexpr IValueT B27 = 1 << 27;
67 static constexpr IValueT L = 1 << 20; // load (or store)
68 static constexpr IValueT W = 1 << 21; // writeback base register
70 static constexpr IValueT B = 1 << 22; // unsigned byte (or word)
71 static constexpr IValueT U = 1 << 23; // positive (or negative)
73 static constexpr IValueT P = 1 << 24; // offset/pre-indexed
77 static constexpr IValueT kConditionShift = 28;
78 static constexpr IValueT kLinkShift = 24;
79 static constexpr IValueT kOpcodeShift = 21;
80 static constexpr IValueT kRdShift = 12;
81 static constexpr IValueT kRmShift = 0;
82 static constexpr IValueT kRnShift = 16;
83 static constexpr IValueT kRsShift = 8;
84 static constexpr IValueT kSShift = 20;
85 static constexpr IValueT kTypeShift = 25;
88 static constexpr IValueT kImmed8Bits = 8;
89 static constexpr IValueT kImmed8Shift = 0;
90 static constexpr IValueT kRotateBits = 4;
91 static constexpr IValueT kRotateShift = 8;
94 static constexpr IValueT kShiftImmShift = 7;
95 static constexpr IValueT kShiftImmBits = 5;
96 static constexpr IValueT kShiftShift = 5;
97 static constexpr IValueT kImmed12Bits = 12;
98 static constexpr IValueT kImm12Shift = 0;
101 static constexpr IValueT kRotationShift = 10;
104 static constexpr IValueT kMemExOpcodeShift = 20;
107 static constexpr IValueT kDivRdShift = 16;
108 static constexpr IValueT kDivRmShift = 8;
109 static constexpr IValueT kDivRnShift = 0;
112 static constexpr IValueT kInstTypeDataRegister = 0; // i.e. 000
113 static constexpr IValueT kInstTypeDataRegShift = 0; // i.e. 000
114 static constexpr IValueT kInstTypeDataImmediate = 1; // i.e. 001
115 static constexpr IValueT kInstTypeMemImmediate = 2; // i.e. 010
116 static constexpr IValueT kInstTypeRegisterShift = 3; // i.e. 011
129 IValueT encodeBool(bool B) { return B ? 1 : 0; } in encodeBool()
131 IValueT encodeRotation(ARM32::AssemblerARM32::RotationValue Value) { in encodeRotation()
132 return static_cast<IValueT>(Value); in encodeRotation()
135 IValueT encodeGPRRegister(RegARM32::GPRRegister Rn) { in encodeGPRRegister()
136 return static_cast<IValueT>(Rn); in encodeGPRRegister()
139 RegARM32::GPRRegister decodeGPRRegister(IValueT R) { in decodeGPRRegister()
143 IValueT encodeCondition(CondARM32::Cond Cond) { in encodeCondition()
144 return static_cast<IValueT>(Cond); in encodeCondition()
147 IValueT encodeShift(OperandARM32::ShiftKind Shift) { in encodeShift()
166 IValueT mask(IValueT Value, IValueT Shift, IValueT Bits) { in mask()
171 bool isBitSet(IValueT Bit, IValueT Value) { return (Value & Bit) == Bit; } in isBitSet()
174 RegARM32::GPRRegister getGPRReg(IValueT Shift, IValueT Value) { in getGPRReg()
178 IValueT getEncodedGPRegNum(const Variable *Var) { in getEncodedGPRegNum()
185 IValueT getEncodedSRegNum(const Variable *Var) { in getEncodedSRegNum()
190 IValueT getEncodedDRegNum(const Variable *Var) { in getEncodedDRegNum()
194 IValueT getEncodedQRegNum(const Variable *Var) { in getEncodedQRegNum()
198 IValueT mapQRegToDReg(IValueT EncodedQReg) { in mapQRegToDReg()
199 IValueT DReg = EncodedQReg << 1; in mapQRegToDReg()
204 IValueT mapQRegToSReg(IValueT EncodedQReg) { in mapQRegToSReg()
205 IValueT SReg = EncodedQReg << 2; in mapQRegToSReg()
210 IValueT getYInRegXXXXY(IValueT RegXXXXY) { return RegXXXXY & 0x1; } in getYInRegXXXXY()
212 IValueT getXXXXInRegXXXXY(IValueT RegXXXXY) { return RegXXXXY >> 1; } in getXXXXInRegXXXXY()
214 IValueT getYInRegYXXXX(IValueT RegYXXXX) { return RegYXXXX >> 4; } in getYInRegYXXXX()
216 IValueT getXXXXInRegYXXXX(IValueT RegYXXXX) { return RegYXXXX & 0x0f; } in getXXXXInRegYXXXX()
219 bool encodeAdvSIMDExpandImm(IValueT Value, Type ElmtTy, IValueT &Op, in encodeAdvSIMDExpandImm()
220 IValueT &Cmode, IValueT &Imm8) { in encodeAdvSIMDExpandImm()
222 constexpr IValueT Imm8Mask = 0xFF; in encodeAdvSIMDExpandImm()
223 if ((Value & IValueT(~Imm8Mask)) != 0) in encodeAdvSIMDExpandImm()
326 IValueT encodeRotatedImm8(IValueT RotateAmt, IValueT Immed8) { in encodeRotatedImm8()
334 IValueT encodeShiftRotateImm5(IValueT Rm, OperandARM32::ShiftKind Shift, in encodeShiftRotateImm5()
343 IValueT encodeShiftRotateReg(IValueT Rm, OperandARM32::ShiftKind Shift, in encodeShiftRotateReg()
344 IValueT Rs) { in encodeShiftRotateReg()
352 EncodedOperand encodeOperand(const Operand *Opnd, IValueT &Value, in encodeOperand()
376 const IValueT Immed8 = FlexImm->getImm(); in encodeOperand()
377 const IValueT Rotate = FlexImm->getRotateAmt(); in encodeOperand()
389 IValueT Rm; in encodeOperand()
393 IValueT Rs; in encodeOperand()
414 const IValueT Immed5 = ShImm->getShAmtImm(); in encodeOperand()
422 IValueT encodeImmRegOffset(IValueT Reg, IOffsetT Offset, in encodeImmRegOffset()
424 IValueT OffsetShift) { in encodeImmRegOffset()
425 IValueT Value = Mode | (Reg << kRnShift); in encodeImmRegOffset()
436 IValueT encodeImmRegOffsetEnc3(IValueT Rn, IOffsetT Imm8, in encodeImmRegOffsetEnc3()
438 IValueT Value = Mode | (Rn << kRnShift); in encodeImmRegOffsetEnc3()
448 IValueT encodeImmRegOffset(EncodedImmAddress ImmEncoding, IValueT Reg, in encodeImmRegOffset()
453 constexpr IValueT NoRightShift = 0; in encodeImmRegOffset()
459 constexpr IValueT RightShift2 = 2; in encodeImmRegOffset()
464 constexpr IValueT NoRightShift = 0; in encodeImmRegOffset()
480 EncodedOperand encodeAddress(const Operand *Opnd, IValueT &Value, in encodeAddress()
501 IValueT Rn = getEncodedGPRegNum(Var); in encodeAddress()
528 IValueT encodeBranchOffset(IOffsetT Offset, IValueT Inst) { in encodeBranchOffset()
540 IValueT encodeRegister(const Operand *OpReg, RegSetWanted WantedRegSet, in encodeRegister()
542 IValueT Reg = 0; in encodeRegister()
549 IValueT encodeGPRegister(const Operand *OpReg, const char *RegName, in encodeGPRegister()
554 IValueT encodeSRegister(const Operand *OpReg, const char *RegName, in encodeSRegister()
559 IValueT encodeDRegister(const Operand *OpReg, const char *RegName, in encodeDRegister()
564 IValueT encodeQRegister(const Operand *OpReg, const char *RegName, in encodeQRegister()
569 void verifyPOrNotW(IValueT Address, const char *InstName) { in verifyPOrNotW()
577 void verifyRegsNotEq(IValueT Reg1, const char *Reg1Name, IValueT Reg2, in verifyRegsNotEq()
586 void verifyRegNotPc(IValueT Reg, const char *RegName, const char *InstName) { in verifyRegNotPc()
590 void verifyAddrRegNotPc(IValueT RegShift, IValueT Address, const char *RegName, in verifyAddrRegNotPc()
599 void verifyRegNotPcWhenSetFlags(IValueT Reg, bool SetFlags, in verifyRegNotPcWhenSetFlags()
611 IValueT encodeSIMDShiftImm6(SIMDShiftType Shift, Type ElmtTy, in encodeSIMDShiftImm6()
612 const IValueT Imm) { in encodeSIMDShiftImm6()
618 const IValueT VshlImm = Imm - MaxShift; in encodeSIMDShiftImm6()
619 const IValueT VshrImm = 2 * MaxShift - Imm; in encodeSIMDShiftImm6()
623 IValueT encodeSIMDShiftImm6(SIMDShiftType Shift, Type ElmtTy, in encodeSIMDShiftImm6()
625 const IValueT Imm = Imm6->getValue(); in encodeSIMDShiftImm6()
638 IValueT Inst = Asm.load<IValueT>(position()); in emit()
654 IValueT AssemblerARM32::encodeElmtType(Type ElmtTy) { in encodeElmtType()
676 const IValueT Inst = Asm->load<IValueT>(position()); in emitOffset()
677 constexpr IValueT Imm16Mask = 0x000F0FFF; in emitOffset()
678 const IValueT Imm16 = offset() & 0xffff; in emitOffset()
701 IValueT Inst = Asm.load<IValueT>(position()); in emit()
712 const IValueT Inst = Asm->load<IValueT>(position()); in emitOffset()
713 constexpr IValueT OffsetMask = 0x00FFFFFF; in emitOffset()
718 constexpr intptr_t InstWidth = sizeof(IValueT); in padWithNop()
766 IOffsetT AssemblerARM32::decodeBranchOffset(IValueT Inst) { in decodeBranchOffset()
778 IValueT Inst = Buffer.load<IValueT>(Position); in bind()
779 Buffer.store<IValueT>(Position, encodeBranchOffset(Dest, Inst)); in bind()
794 void AssemblerARM32::emitType01(CondARM32::Cond Cond, IValueT InstType, in emitType01()
795 IValueT Opcode, bool SetFlags, IValueT Rn, in emitType01()
796 IValueT Rd, IValueT Imm12, in emitType01()
807 const IValueT Encoding = (encodeCondition(Cond) << kConditionShift) | in emitType01()
814 void AssemblerARM32::emitType01(CondARM32::Cond Cond, IValueT Opcode, in emitType01()
818 IValueT Rd = encodeGPRegister(OpRd, "Rd", InstName); in emitType01()
819 IValueT Rn = encodeGPRegister(OpRn, "Rn", InstName); in emitType01()
823 void AssemblerARM32::emitType01(CondARM32::Cond Cond, IValueT Opcode, in emitType01()
824 IValueT Rd, IValueT Rn, const Operand *OpSrc1, in emitType01()
827 IValueT Src1Value; in emitType01()
840 constexpr IValueT Imm5 = 0; in emitType01()
854 IValueT RotateAmt; in emitType01()
855 IValueT Imm8; in emitType01()
892 IValueT Encoding = static_cast<int32_t>(Cond) << kConditionShift | in emitType05()
911 void AssemblerARM32::emitCompareOp(CondARM32::Cond Cond, IValueT Opcode, in emitCompareOp()
928 constexpr IValueT Rd = RegARM32::Encoded_Reg_r0; in emitCompareOp()
929 IValueT Rn = encodeGPRegister(OpRn, "Rn", InstName); in emitCompareOp()
933 void AssemblerARM32::emitMemOp(CondARM32::Cond Cond, IValueT InstType, in emitMemOp()
934 bool IsLoad, bool IsByte, IValueT Rt, in emitMemOp()
935 IValueT Address) { in emitMemOp()
938 const IValueT Encoding = (encodeCondition(Cond) << kConditionShift) | in emitMemOp()
945 IValueT Rt, const Operand *OpAddress, in emitMemOp()
947 IValueT Address; in emitMemOp()
1001 void AssemblerARM32::emitMemOpEnc3(CondARM32::Cond Cond, IValueT Opcode, in emitMemOpEnc3()
1002 IValueT Rt, const Operand *OpAddress, in emitMemOpEnc3()
1005 IValueT Address; in emitMemOpEnc3()
1025 const IValueT Encoding = (encodeCondition(Cond) << kConditionShift) | in emitMemOpEnc3()
1052 const IValueT Encoding = (encodeCondition(Cond) << kConditionShift) | in emitMemOpEnc3()
1060 void AssemblerARM32::emitDivOp(CondARM32::Cond Cond, IValueT Opcode, IValueT Rd, in emitDivOp()
1061 IValueT Rn, IValueT Rm) { in emitDivOp()
1066 const IValueT Encoding = Opcode | (encodeCondition(Cond) << kConditionShift) | in emitDivOp()
1077 const IValueT Rt = encodeGPRegister(OpRt, "Rt", InstName); in emitInsertExtractInt()
1078 IValueT Dn = mapQRegToDReg(encodeQRegister(OpQn, "Qn", InstName)); in emitInsertExtractInt()
1083 IValueT Opcode1 = 0; in emitInsertExtractInt()
1084 IValueT Opcode2 = 0; in emitInsertExtractInt()
1108 const IValueT Encoding = B27 | B26 | B25 | B11 | B9 | B8 | B4 | in emitInsertExtractInt()
1117 void AssemblerARM32::emitMoveSS(CondARM32::Cond Cond, IValueT Sd, IValueT Sm) { in emitMoveSS()
1122 constexpr IValueT VmovssOpcode = B23 | B21 | B20 | B6; in emitMoveSS()
1123 constexpr IValueT S0 = 0; in emitMoveSS()
1127 void AssemblerARM32::emitMulOp(CondARM32::Cond Cond, IValueT Opcode, IValueT Rd, in emitMulOp()
1128 IValueT Rn, IValueT Rm, IValueT Rs, in emitMulOp()
1135 IValueT Encoding = Opcode | (encodeCondition(Cond) << kConditionShift) | in emitMulOp()
1144 IValueT BaseReg, IValueT Registers) { in emitMultiMemOp()
1148 IValueT Encoding = (encodeCondition(Cond) << kConditionShift) | B27 | in emitMultiMemOp()
1154 void AssemblerARM32::emitSignExtend(CondARM32::Cond Cond, IValueT Opcode, in emitSignExtend()
1157 IValueT Rd = encodeGPRegister(OpRd, "Rd", InstName); in emitSignExtend()
1158 IValueT Rm = encodeGPRegister(OpSrc0, "Rm", InstName); in emitSignExtend()
1161 constexpr IValueT Rn = RegARM32::Encoded_Reg_pc; in emitSignExtend()
1190 IValueT Rot = encodeRotation(Rotation); in emitSignExtend()
1194 IValueT Encoding = (encodeCondition(Cond) << kConditionShift) | Opcode | in emitSignExtend()
1200 void AssemblerARM32::emitSIMDBase(IValueT Opcode, IValueT Dd, IValueT Dn, in emitSIMDBase()
1201 IValueT Dm, bool UseQRegs, bool IsFloatTy) { in emitSIMDBase()
1202 const IValueT Encoding = in emitSIMDBase()
1211 void AssemblerARM32::emitSIMD(IValueT Opcode, Type ElmtTy, IValueT Dd, in emitSIMD()
1212 IValueT Dn, IValueT Dm, bool UseQRegs) { in emitSIMD()
1213 constexpr IValueT ElmtShift = 20; in emitSIMD()
1214 const IValueT ElmtSize = encodeElmtType(ElmtTy); in emitSIMD()
1220 void AssemblerARM32::emitSIMDqqqBase(IValueT Opcode, const Operand *OpQd, in emitSIMDqqqBase()
1223 const IValueT Qd = encodeQRegister(OpQd, "Qd", OpcodeName); in emitSIMDqqqBase()
1224 const IValueT Qn = encodeQRegister(OpQn, "Qn", OpcodeName); in emitSIMDqqqBase()
1225 const IValueT Qm = encodeQRegister(OpQm, "Qm", OpcodeName); in emitSIMDqqqBase()
1231 void AssemblerARM32::emitSIMDqqq(IValueT Opcode, Type ElmtTy, in emitSIMDqqq()
1234 constexpr IValueT ElmtShift = 20; in emitSIMDqqq()
1235 const IValueT ElmtSize = encodeElmtType(ElmtTy); in emitSIMDqqq()
1241 void AssemblerARM32::emitSIMDShiftqqc(IValueT Opcode, const Operand *OpQd, in emitSIMDShiftqqc()
1242 const Operand *OpQm, const IValueT Imm6, in emitSIMDShiftqqc()
1244 const IValueT Qd = encodeQRegister(OpQd, "Qd", OpcodeName); in emitSIMDShiftqqc()
1245 const IValueT Qn = 0; in emitSIMDShiftqqc()
1246 const IValueT Qm = encodeQRegister(OpQm, "Qm", OpcodeName); in emitSIMDShiftqqc()
1249 constexpr IValueT ElmtShift = 16; in emitSIMDShiftqqc()
1254 void AssemblerARM32::emitSIMDCvtqq(IValueT Opcode, const Operand *OpQd, in emitSIMDCvtqq()
1257 const IValueT SIMDOpcode = in emitSIMDCvtqq()
1261 const IValueT Qd = encodeQRegister(OpQd, "Qd", OpcodeName); in emitSIMDCvtqq()
1262 constexpr IValueT Qn = 0; in emitSIMDCvtqq()
1263 const IValueT Qm = encodeQRegister(OpQm, "Qm", OpcodeName); in emitSIMDCvtqq()
1268 void AssemblerARM32::emitVFPddd(CondARM32::Cond Cond, IValueT Opcode, in emitVFPddd()
1269 IValueT Dd, IValueT Dn, IValueT Dm) { in emitVFPddd()
1274 constexpr IValueT VFPOpcode = B27 | B26 | B25 | B11 | B9 | B8; in emitVFPddd()
1275 const IValueT Encoding = in emitVFPddd()
1283 void AssemblerARM32::emitVFPddd(CondARM32::Cond Cond, IValueT Opcode, in emitVFPddd()
1286 IValueT Dd = encodeDRegister(OpDd, "Dd", InstName); in emitVFPddd()
1287 IValueT Dn = encodeDRegister(OpDn, "Dn", InstName); in emitVFPddd()
1288 IValueT Dm = encodeDRegister(OpDm, "Dm", InstName); in emitVFPddd()
1292 void AssemblerARM32::emitVFPsss(CondARM32::Cond Cond, IValueT Opcode, in emitVFPsss()
1293 IValueT Sd, IValueT Sn, IValueT Sm) { in emitVFPsss()
1298 constexpr IValueT VFPOpcode = B27 | B26 | B25 | B11 | B9; in emitVFPsss()
1299 const IValueT Encoding = in emitVFPsss()
1307 void AssemblerARM32::emitVFPsss(CondARM32::Cond Cond, IValueT Opcode, in emitVFPsss()
1310 const IValueT Sd = encodeSRegister(OpSd, "Sd", InstName); in emitVFPsss()
1311 const IValueT Sn = encodeSRegister(OpSn, "Sn", InstName); in emitVFPsss()
1312 const IValueT Sm = encodeSRegister(OpSm, "Sm", InstName); in emitVFPsss()
1331 constexpr IValueT AdcOpcode = B2 | B0; // 0101 in adc()
1355 constexpr IValueT Add = B2; // 0100 in add()
1375 constexpr IValueT And = 0; // 0000 in and_()
1389 const IValueT Encoding = (CondARM32::AL << kConditionShift) | B24 | B21 | in bkpt()
1409 constexpr IValueT BicOpcode = B3 | B2 | B1; // i.e. 1110 in bic()
1422 constexpr IValueT Immed = 0; in bl()
1434 IValueT Rm = encodeGPRegister(Target, "Rm", BlxName); in blx()
1448 const IValueT Encoding = (encodeCondition(Cond) << kConditionShift) | B24 | in bx()
1463 IValueT Rd = encodeGPRegister(OpRd, RdName, ClzName); in clz()
1466 IValueT Rm = encodeGPRegister(OpSrc, RmName, ClzName); in clz()
1470 constexpr IValueT PredefinedBits = in clz()
1472 const IValueT Encoding = PredefinedBits | (Cond << kConditionShift) | in clz()
1491 constexpr IValueT CmnOpcode = B3 | B1 | B0; // ie. 1011 in cmn()
1509 constexpr IValueT CmpOpcode = B3 | B1; // ie. 1010 in cmp()
1513 void AssemblerARM32::dmb(IValueT Option) { in dmb()
1519 const IValueT Encoding = in dmb()
1541 constexpr IValueT EorOpcode = B0; // 0001 in eor()
1550 IValueT Rt = encodeGPRegister(OpRt, "Rt", LdrName); in ldr()
1619 const Operand *OpRd, IValueT Rt, in emitMemExOp()
1623 IValueT Rd = encodeGPRegister(OpRd, "Rd", InstName); in emitMemExOp()
1624 IValueT MemExOpcode = IsLoad ? B0 : 0; in emitMemExOp()
1641 IValueT AddressRn; in emitMemExOp()
1650 IValueT Encoding = (Cond << kConditionShift) | B24 | B23 | B11 | B10 | B9 | in emitMemExOp()
1681 constexpr IValueT Rm = RegARM32::Encoded_Reg_pc; in ldrex()
1690 constexpr IValueT ShiftOpcode = B3 | B2 | B0; // 1101 in emitShift()
1691 IValueT Rd = encodeGPRegister(OpRd, "Rd", InstName); in emitShift()
1692 IValueT Rm = encodeGPRegister(OpRm, "Rm", InstName); in emitShift()
1693 IValueT Value; in emitShift()
1704 constexpr IValueT Rn = 0; // Rn field is not used. in emitShift()
1716 constexpr IValueT Rn = 0; // Rn field is not used. in emitShift()
1717 IValueT Rs = encodeGPRegister(OpSrc1, "Rs", InstName); in emitShift()
1764 IValueT Rd = encodeGPRegister(OpRd, "Rd", MovName); in mov()
1766 constexpr IValueT Rn = 0; in mov()
1767 constexpr IValueT MovOpcode = B3 | B2 | B0; // 1101. in mov()
1775 IValueT Opcode = B25 | B24 | (IsMovW ? 0 : B22); in emitMovwt()
1776 IValueT Rd = encodeGPRegister(OpRd, "Rd", MovName); in emitMovwt()
1777 IValueT Imm16; in emitMovwt()
1789 const IValueT Encoding = encodeCondition(Cond) << kConditionShift | Opcode | in emitMovwt()
1833 IValueT Rd = encodeGPRegister(OpRd, "Rd", MvnName); in mvn()
1834 constexpr IValueT MvnOpcode = B3 | B2 | B1 | B0; // i.e. 1111 in mvn()
1835 constexpr IValueT Rn = 0; in mvn()
1847 const IValueT Encoding = (encodeCondition(Cond) << kConditionShift) | B25 | in nop()
1867 constexpr IValueT SbcOpcode = B2 | B1; // 0110 in sbc()
1880 IValueT Rd = encodeGPRegister(OpRd, "Rd", SdivName); in sdiv()
1881 IValueT Rn = encodeGPRegister(OpRn, "Rn", SdivName); in sdiv()
1882 IValueT Rm = encodeGPRegister(OpSrc1, "Rm", SdivName); in sdiv()
1887 constexpr IValueT SdivOpcode = 0; in sdiv()
1895 IValueT Rt = encodeGPRegister(OpRt, "Rt", StrName); in str()
1979 IValueT Rt = encodeGPRegister(OpRt, "Rt", StrexName); in strex()
2000 constexpr IValueT OrrOpcode = B3 | B2; // i.e. 1100 in orr()
2011 IValueT Rt = encodeGPRegister(OpRt, "Rt", Pop); in pop()
2017 constexpr IValueT NoShiftRight = 0; in pop()
2018 IValueT Address = in pop()
2024 void AssemblerARM32::popList(const IValueT Registers, CondARM32::Cond Cond) { in popList()
2040 IValueT Rt = encodeGPRegister(OpRt, "Rt", Push); in push()
2046 constexpr IValueT NoShiftRight = 0; in push()
2047 IValueT Address = in push()
2053 void AssemblerARM32::pushList(const IValueT Registers, CondARM32::Cond Cond) { in pushList()
2072 IValueT Rd = encodeGPRegister(OpRd, "Rd", MlaName); in mla()
2073 IValueT Rn = encodeGPRegister(OpRn, "Rn", MlaName); in mla()
2074 IValueT Rm = encodeGPRegister(OpRm, "Rm", MlaName); in mla()
2075 IValueT Ra = encodeGPRegister(OpRa, "Ra", MlaName); in mla()
2080 constexpr IValueT MlaOpcode = B21; in mla()
2090 IValueT Rd = encodeGPRegister(OpRd, "Rd", MlsName); in mls()
2091 IValueT Rn = encodeGPRegister(OpRn, "Rn", MlsName); in mls()
2092 IValueT Rm = encodeGPRegister(OpRm, "Rm", MlsName); in mls()
2093 IValueT Ra = encodeGPRegister(OpRa, "Ra", MlsName); in mls()
2098 constexpr IValueT MlsOpcode = B22 | B21; in mls()
2113 IValueT Rd = encodeGPRegister(OpRd, "Rd", MulName); in mul()
2114 IValueT Rn = encodeGPRegister(OpRn, "Rn", MulName); in mul()
2115 IValueT Rm = encodeGPRegister(OpSrc1, "Rm", MulName); in mul()
2120 constexpr IValueT MulOpcode = 0; in mul()
2124 void AssemblerARM32::emitRdRm(CondARM32::Cond Cond, IValueT Opcode, in emitRdRm()
2127 IValueT Rd = encodeGPRegister(OpRd, "Rd", InstName); in emitRdRm()
2128 IValueT Rm = encodeGPRegister(OpRm, "Rm", InstName); in emitRdRm()
2129 IValueT Encoding = in emitRdRm()
2141 constexpr IValueT RbitOpcode = B26 | B25 | B23 | B22 | B21 | B20 | B19 | B18 | in rbit()
2153 constexpr IValueT RevOpcode = B26 | B25 | B23 | B21 | B20 | B19 | B18 | B17 | in rev()
2173 constexpr IValueT RsbOpcode = B1 | B0; // 0011 in rsb()
2199 constexpr IValueT RscOpcode = B2 | B1 | B0; // i.e. 0111. in rsc()
2207 constexpr IValueT SxtOpcode = B26 | B25 | B23 | B21; in sxt()
2230 constexpr IValueT SubOpcode = B1; // 0010 in sub()
2270 constexpr IValueT TstOpcode = B3; // ie. 1000 in tst()
2282 IValueT Rd = encodeGPRegister(OpRd, "Rd", UdivName); in udiv()
2283 IValueT Rn = encodeGPRegister(OpRn, "Rn", UdivName); in udiv()
2284 IValueT Rm = encodeGPRegister(OpSrc1, "Rm", UdivName); in udiv()
2289 constexpr IValueT UdivOpcode = B21; in udiv()
2302 IValueT RdLo = encodeGPRegister(OpRdLo, "RdLo", UmullName); in umull()
2303 IValueT RdHi = encodeGPRegister(OpRdHi, "RdHi", UmullName); in umull()
2304 IValueT Rn = encodeGPRegister(OpRn, "Rn", UmullName); in umull()
2305 IValueT Rm = encodeGPRegister(OpRm, "Rm", UmullName); in umull()
2311 constexpr IValueT UmullOpcode = B23; in umull()
2319 constexpr IValueT UxtOpcode = B26 | B25 | B23 | B22 | B21; in uxt()
2330 IValueT Sd = encodeSRegister(OpSd, "Sd", Vabss); in vabss()
2331 IValueT Sm = encodeSRegister(OpSm, "Sm", Vabss); in vabss()
2332 constexpr IValueT S0 = 0; in vabss()
2333 constexpr IValueT VabssOpcode = B23 | B21 | B20 | B7 | B6; in vabss()
2344 const IValueT Dd = encodeDRegister(OpDd, "Dd", Vabsd); in vabsd()
2345 const IValueT Dm = encodeDRegister(OpDm, "Dm", Vabsd); in vabsd()
2346 constexpr IValueT D0 = 0; in vabsd()
2347 constexpr IValueT VabsdOpcode = B23 | B21 | B20 | B7 | B6; in vabsd()
2360 const IValueT Dd = mapQRegToDReg(encodeQRegister(OpQd, "Qd", Vabsq)); in vabsq()
2361 const IValueT Dm = mapQRegToDReg(encodeQRegister(OpQm, "Qm", Vabsq)); in vabsq()
2362 constexpr IValueT Dn = 0; in vabsq()
2363 const IValueT VabsqOpcode = in vabsq()
2377 constexpr IValueT VaddsOpcode = B21 | B20; in vadds()
2391 constexpr IValueT VaddqiOpcode = B11; in vaddqi()
2403 constexpr IValueT VaddqfOpcode = B11 | B8; in vaddqf()
2416 constexpr IValueT VadddOpcode = B21 | B20; in vaddd()
2427 constexpr IValueT VandqOpcode = B8 | B4; in vandq()
2439 constexpr IValueT VbslqOpcode = B24 | B20 | B8 | B4; in vbslq()
2452 constexpr IValueT VceqOpcode = B24 | B11 | B4; in vceqqi()
2463 constexpr IValueT VceqOpcode = B11 | B10 | B9; in vceqqs()
2476 constexpr IValueT VcgeOpcode = B9 | B8 | B4; in vcgeqi()
2488 constexpr IValueT VcgeOpcode = B24 | B9 | B8 | B4; in vcugeqi()
2499 constexpr IValueT VcgeOpcode = B24 | B11 | B10 | B9; in vcgeqs()
2512 constexpr IValueT VcgeOpcode = B9 | B8; in vcgtqi()
2524 constexpr IValueT VcgeOpcode = B24 | B9 | B8; in vcugtqi()
2535 constexpr IValueT VcgeOpcode = B24 | B21 | B11 | B10 | B9; in vcgtqs()
2543 IValueT Dd = encodeDRegister(OpDd, "Dd", Vcmpd); in vcmpd()
2544 IValueT Dm = encodeDRegister(OpDm, "Dm", Vcmpd); in vcmpd()
2545 constexpr IValueT VcmpdOpcode = B23 | B21 | B20 | B18 | B6; in vcmpd()
2546 constexpr IValueT Dn = 0; in vcmpd()
2552 IValueT Dd = encodeDRegister(OpDd, "Dd", Vcmpdz); in vcmpdz()
2553 constexpr IValueT VcmpdzOpcode = B23 | B21 | B20 | B18 | B16 | B6; in vcmpdz()
2554 constexpr IValueT Dn = 0; in vcmpdz()
2555 constexpr IValueT Dm = 0; in vcmpdz()
2562 IValueT Sd = encodeSRegister(OpSd, "Sd", Vcmps); in vcmps()
2563 IValueT Sm = encodeSRegister(OpSm, "Sm", Vcmps); in vcmps()
2564 constexpr IValueT VcmpsOpcode = B23 | B21 | B20 | B18 | B6; in vcmps()
2565 constexpr IValueT Sn = 0; in vcmps()
2571 IValueT Sd = encodeSRegister(OpSd, "Sd", Vcmpsz); in vcmpsz()
2572 constexpr IValueT VcmpszOpcode = B23 | B21 | B20 | B18 | B16 | B6; in vcmpsz()
2573 constexpr IValueT Sn = 0; in vcmpsz()
2574 constexpr IValueT Sm = 0; in vcmpsz()
2578 void AssemblerARM32::emitVFPsd(CondARM32::Cond Cond, IValueT Opcode, IValueT Sd, in emitVFPsd()
2579 IValueT Dm) { in emitVFPsd()
2583 constexpr IValueT VFPOpcode = B27 | B26 | B25 | B11 | B9; in emitVFPsd()
2584 const IValueT Encoding = in emitVFPsd()
2599 IValueT Dd = encodeDRegister(OpDd, "Dd", Vcvtdi); in vcvtdi()
2600 IValueT Sm = encodeSRegister(OpSm, "Sm", Vcvtdi); in vcvtdi()
2601 constexpr IValueT VcvtdiOpcode = B23 | B21 | B20 | B19 | B8 | B7 | B6; in vcvtdi()
2613 IValueT Dd = encodeDRegister(OpDd, "Dd", Vcvtdu); in vcvtdu()
2614 IValueT Sm = encodeSRegister(OpSm, "Sm", Vcvtdu); in vcvtdu()
2615 constexpr IValueT VcvtduOpcode = B23 | B21 | B20 | B19 | B8 | B6; in vcvtdu()
2622 IValueT Sd = encodeSRegister(OpSd, "Sd", Vcvtsd); in vcvtsd()
2623 IValueT Dm = encodeDRegister(OpDm, "Dm", Vcvtsd); in vcvtsd()
2624 constexpr IValueT VcvtsdOpcode = in vcvtsd()
2637 IValueT Sd = encodeSRegister(OpSd, "Sd", Vcvtis); in vcvtis()
2638 IValueT Sm = encodeSRegister(OpSm, "Sm", Vcvtis); in vcvtis()
2639 constexpr IValueT VcvtisOpcode = B23 | B21 | B20 | B19 | B18 | B16 | B7 | B6; in vcvtis()
2640 constexpr IValueT S0 = 0; in vcvtis()
2652 IValueT Sd = encodeSRegister(OpSd, "Sd", Vcvtid); in vcvtid()
2653 IValueT Dm = encodeDRegister(OpDm, "Dm", Vcvtid); in vcvtid()
2654 constexpr IValueT VcvtidOpcode = in vcvtid()
2667 IValueT Sd = encodeSRegister(OpSd, "Sd", Vcvtsi); in vcvtsi()
2668 IValueT Sm = encodeSRegister(OpSm, "Sm", Vcvtsi); in vcvtsi()
2669 constexpr IValueT VcvtsiOpcode = B23 | B21 | B20 | B19 | B7 | B6; in vcvtsi()
2670 constexpr IValueT S0 = 0; in vcvtsi()
2682 IValueT Sd = encodeSRegister(OpSd, "Sd", Vcvtsu); in vcvtsu()
2683 IValueT Sm = encodeSRegister(OpSm, "Sm", Vcvtsu); in vcvtsu()
2684 constexpr IValueT VcvtsuOpcode = B23 | B21 | B20 | B19 | B6; in vcvtsu()
2685 constexpr IValueT S0 = 0; in vcvtsu()
2697 IValueT Sd = encodeSRegister(OpSd, "Sd", Vcvtud); in vcvtud()
2698 IValueT Dm = encodeDRegister(OpDm, "Dm", Vcvtud); in vcvtud()
2699 constexpr IValueT VcvtudOpcode = B23 | B21 | B20 | B19 | B18 | B8 | B7 | B6; in vcvtud()
2711 IValueT Sd = encodeSRegister(OpSd, "Sd", Vcvtus); in vcvtus()
2712 IValueT Sm = encodeSRegister(OpSm, "Sm", Vcvtus); in vcvtus()
2713 constexpr IValueT VcvtsiOpcode = B23 | B21 | B20 | B19 | B18 | B7 | B6; in vcvtus()
2714 constexpr IValueT S0 = 0; in vcvtus()
2725 constexpr IValueT VcvtqsiOpcode = B8; in vcvtqsi()
2736 constexpr IValueT VcvtqsuOpcode = B8 | B7; in vcvtqsu()
2747 constexpr IValueT VcvtqisOpcode = 0; in vcvtqis()
2758 constexpr IValueT VcvtqusOpcode = B7; in vcvtqus()
2762 void AssemblerARM32::emitVFPds(CondARM32::Cond Cond, IValueT Opcode, IValueT Dd, in emitVFPds()
2763 IValueT Sm) { in emitVFPds()
2767 constexpr IValueT VFPOpcode = B27 | B26 | B25 | B11 | B9; in emitVFPds()
2768 const IValueT Encoding = in emitVFPds()
2778 IValueT Dd = encodeDRegister(OpDd, "Dd", Vcvtds); in vcvtds()
2779 IValueT Sm = encodeSRegister(OpSm, "Sm", Vcvtds); in vcvtds()
2780 constexpr IValueT VcvtdsOpcode = B23 | B21 | B20 | B18 | B17 | B16 | B7 | B6; in vcvtds()
2792 constexpr IValueT VdivsOpcode = B23; in vdivs()
2804 constexpr IValueT VdivdOpcode = B23; in vdivd()
2815 IValueT Dd = encodeDRegister(OpDd, "Dd", Veord); in veord()
2816 IValueT Dn = encodeDRegister(OpDn, "Dn", Veord); in veord()
2817 IValueT Dm = encodeDRegister(OpDm, "Dm", Veord); in veord()
2818 const IValueT Encoding = in veord()
2834 constexpr IValueT VeorqOpcode = B24 | B8 | B4; in veorq()
2846 IValueT Dd = encodeDRegister(OpDd, "Dd", Vldrd); in vldrd()
2848 IValueT Address; in vldrd()
2853 IValueT Encoding = B27 | B26 | B24 | B20 | B11 | B9 | B8 | in vldrd()
2871 IValueT Dd = mapQRegToDReg(encodeQRegister(OpQd, "Qd", Vldrd)); in vldrq()
2873 IValueT Address; in vldrq()
2878 IValueT Encoding = B27 | B26 | B24 | B20 | B11 | B9 | B8 | in vldrq()
2893 IValueT Sd = encodeSRegister(OpSd, "Sd", Vldrs); in vldrs()
2895 IValueT Address; in vldrs()
2900 IValueT Encoding = B27 | B26 | B24 | B20 | B11 | B9 | in vldrs()
2907 void AssemblerARM32::emitVMem1Op(IValueT Opcode, IValueT Dd, IValueT Rn, in emitVMem1Op()
2908 IValueT Rm, DRegListSize NumDRegs, in emitVMem1Op()
2909 size_t ElmtSize, IValueT Align, in emitVMem1Op()
2912 IValueT EncodedElmtSize; in emitVMem1Op()
2932 const IValueT Encoding = in emitVMem1Op()
2940 void AssemblerARM32::emitVMem1Op(IValueT Opcode, IValueT Dd, IValueT Rn, in emitVMem1Op()
2941 IValueT Rm, size_t ElmtSize, IValueT Align, in emitVMem1Op()
2944 IValueT EncodedElmtSize; in emitVMem1Op()
2964 const IValueT Encoding = in emitVMem1Op()
2981 const IValueT Qd = encodeQRegister(OpQd, "Qd", Vld1qr); in vld1qr()
2982 const IValueT Dd = mapQRegToDReg(Qd); in vld1qr()
2983 IValueT Address; in vld1qr()
2987 const IValueT Rn = mask(Address, kRnShift, 4); in vld1qr()
2988 constexpr IValueT Rm = RegARM32::Reg_pc; in vld1qr()
2989 constexpr IValueT Opcode = B26 | B21; in vld1qr()
2990 constexpr IValueT Align = 0; // use default alignment. in vld1qr()
3011 const IValueT Qd = encodeQRegister(OpQd, "Qd", Vld1qr); in vld1()
3012 const IValueT Dd = mapQRegToDReg(Qd); in vld1()
3013 IValueT Address; in vld1()
3017 const IValueT Rn = mask(Address, kRnShift, 4); in vld1()
3018 constexpr IValueT Rm = RegARM32::Reg_pc; in vld1()
3019 constexpr IValueT Opcode = B26 | B23 | B21; in vld1()
3020 constexpr IValueT Align = 0; // use default alignment. in vld1()
3030 const IValueT Dd = mapQRegToDReg(encodeQRegister(OpQd, "Qd", Vmovc)); in vmovqc()
3031 IValueT Value = Imm->getValue(); in vmovqc()
3036 IValueT Op; in vmovqc()
3037 IValueT Cmode; in vmovqc()
3038 IValueT Imm8; in vmovqc()
3045 const IValueT Encoding = in vmovqc()
3062 IValueT Dd = encodeSRegister(OpDd, "Dd", Vmovd); in vmovd()
3063 IValueT Imm8 = OpFpImm->getModifiedImm(); in vmovd()
3065 constexpr IValueT VmovsOpcode = B23 | B21 | B20 | B8; in vmovd()
3066 IValueT OpcodePlusImm8 = VmovsOpcode | ((Imm8 >> 4) << 16) | (Imm8 & 0xf); in vmovd()
3067 constexpr IValueT D0 = 0; in vmovd()
3078 IValueT Dd = encodeSRegister(OpDd, "Dd", Vmovdd); in vmovdd()
3079 IValueT Dm = encodeSRegister(OpDm, "Dm", Vmovdd); in vmovdd()
3080 constexpr IValueT VmovddOpcode = B23 | B21 | B20 | B6; in vmovdd()
3081 constexpr IValueT D0 = 0; in vmovdd()
3094 IValueT Dm = encodeDRegister(OpDm, "Dm", Vmovdrr); in vmovdrr()
3095 IValueT Rt = encodeGPRegister(OpRt, "Rt", Vmovdrr); in vmovdrr()
3096 IValueT Rt2 = encodeGPRegister(OpRt2, "Rt", Vmovdrr); in vmovdrr()
3103 IValueT Encoding = B27 | B26 | B22 | B11 | B9 | B8 | B4 | in vmovdrr()
3123 IValueT Sd = mapQRegToSReg(encodeQRegister(OpQd, "Qd", Vmovqis)) + Index; in vmovqis()
3124 IValueT Sm = encodeSRegister(OpSm, "Sm", Vmovqis); in vmovqis()
3146 IValueT Rt = encodeGPRegister(OpRt, "Rt", Vmovrrd); in vmovrrd()
3147 IValueT Rt2 = encodeGPRegister(OpRt2, "Rt", Vmovrrd); in vmovrrd()
3148 IValueT Dm = encodeDRegister(OpDm, "Dm", Vmovrrd); in vmovrrd()
3155 IValueT Encoding = B27 | B26 | B22 | B20 | B11 | B9 | B8 | B4 | in vmovrrd()
3171 IValueT Rt = encodeGPRegister(OpRt, "Rt", Vmovrs); in vmovrs()
3172 IValueT Sn = encodeSRegister(OpSn, "Sn", Vmovrs); in vmovrs()
3174 IValueT Encoding = (encodeCondition(Cond) << kConditionShift) | B27 | B26 | in vmovrs()
3188 IValueT Sd = encodeSRegister(OpSd, "Sd", Vmovs); in vmovs()
3189 IValueT Imm8 = OpFpImm->getModifiedImm(); in vmovs()
3191 constexpr IValueT VmovsOpcode = B23 | B21 | B20; in vmovs()
3192 IValueT OpcodePlusImm8 = VmovsOpcode | ((Imm8 >> 4) << 16) | (Imm8 & 0xf); in vmovs()
3193 constexpr IValueT S0 = 0; in vmovs()
3200 IValueT Sd = encodeSRegister(OpSd, "Sd", Vmovss); in vmovss()
3201 IValueT Sm = encodeSRegister(OpSm, "Sm", Vmovss); in vmovss()
3208 const IValueT Sd = encodeSRegister(OpSd, "Sd", Vmovsqi); in vmovsqi()
3210 const IValueT Sm = in vmovsqi()
3224 IValueT Sn = encodeSRegister(OpSn, "Sn", Vmovsr); in vmovsr()
3225 IValueT Rt = encodeGPRegister(OpRt, "Rt", Vmovsr); in vmovsr()
3229 IValueT Encoding = (encodeCondition(Cond) << kConditionShift) | B27 | B26 | in vmovsr()
3243 constexpr IValueT VmladOpcode = 0; in vmlad()
3255 constexpr IValueT VmlasOpcode = 0; in vmlas()
3267 constexpr IValueT VmladOpcode = B6; in vmlsd()
3279 constexpr IValueT VmlasOpcode = B6; in vmlss()
3290 IValueT Encoding = B27 | B26 | B25 | B23 | B22 | B21 | B20 | B16 | B15 | B14 | in vmrsAPSR_nzcv()
3304 constexpr IValueT VmulsOpcode = B21; in vmuls()
3316 constexpr IValueT VmuldOpcode = B21; in vmuld()
3331 constexpr IValueT VmulqiOpcode = B11 | B8 | B4; in vmulqi()
3350 constexpr IValueT ElmtShift = 20; in vmulh()
3351 const IValueT ElmtSize = encodeElmtType(ElmtTy); in vmulh()
3354 const IValueT VmullOpcode = in vmulh()
3357 const IValueT Qd = encodeQRegister(OpQd, "Qd", Vmull); in vmulh()
3358 const IValueT Qn = encodeQRegister(OpQn, "Qn", Vmull); in vmulh()
3359 const IValueT Qm = encodeQRegister(OpQm, "Qm", Vmull); in vmulh()
3361 const IValueT Dd = mapQRegToDReg(Qd); in vmulh()
3362 const IValueT Dn = mapQRegToDReg(Qn); in vmulh()
3363 const IValueT Dm = mapQRegToDReg(Qm); in vmulh()
3371 constexpr IValueT VshrnOpcode = B25 | B23 | B11 | B4; in vmulh()
3372 const IValueT Imm6 = encodeSIMDShiftImm6(ST_Vshr, IceType_i16, 16); in vmulh()
3373 constexpr IValueT ImmShift = 16; in vmulh()
3393 constexpr IValueT ElmtShift = 20; in vmlap()
3394 const IValueT ElmtSize = encodeElmtType(ElmtTy); in vmlap()
3398 const IValueT VmullOpcode = in vmlap()
3401 const IValueT Dd = mapQRegToDReg(encodeQRegister(OpQd, "Qd", Vmull)); in vmlap()
3402 const IValueT Dn = mapQRegToDReg(encodeQRegister(OpQn, "Qn", Vmull)); in vmlap()
3403 const IValueT Dm = mapQRegToDReg(encodeQRegister(OpQm, "Qm", Vmull)); in vmlap()
3416 const IValueT VpaddOpcode = in vmlap()
3422 IValueT Idx) { in vdup()
3430 const IValueT VdupOpcode = B25 | B24 | B23 | B21 | B20 | B11 | B10; in vdup()
3432 const IValueT Dd = mapQRegToDReg(encodeQRegister(OpQd, "Qd", Vdup)); in vdup()
3433 const IValueT Dn = mapQRegToDReg(encodeQRegister(OpQn, "Qn", Vdup)); in vdup()
3438 IValueT Imm4 = 0; in vdup()
3478 const IValueT Dd = mapQRegToDReg(encodeQRegister(OpQd, "Qd", Vzip)); in vzip()
3479 const IValueT Dn = mapQRegToDReg(encodeQRegister(OpQn, "Qn", Vzip)); in vzip()
3480 const IValueT Dm = mapQRegToDReg(encodeQRegister(OpQm, "Qm", Vzip)); in vzip()
3487 constexpr IValueT VmovOpcode = B25 | B21 | B8 | B4; in vzip()
3496 constexpr IValueT ElmtShift = 18; in vzip()
3497 const IValueT ElmtSize = encodeElmtType(ElmtTy); in vzip()
3501 constexpr IValueT VzipOpcode = B25 | B24 | B23 | B21 | B20 | B17 | B8 | B7; in vzip()
3506 constexpr IValueT VtrnOpcode = B25 | B24 | B23 | B21 | B20 | B17 | B7; in vzip()
3520 constexpr IValueT VmulqfOpcode = B24 | B11 | B8 | B4; in vmulqf()
3532 constexpr IValueT VmvnOpcode = B24 | B23 | B21 | B20 | B10 | B8 | B7; in vmvnq()
3533 const IValueT Qd = encodeQRegister(OpQd, "Qd", Vmvn); in vmvnq()
3534 constexpr IValueT Qn = 0; in vmvnq()
3535 const IValueT Qm = encodeQRegister(OpQm, "Qm", Vmvn); in vmvnq()
3553 const IValueT Dd = mapQRegToDReg(encodeQRegister(OpQd, "Qd", Vmov)); in vmovlq()
3554 const IValueT Dn = mapQRegToDReg(encodeQRegister(OpQn, "Qn", Vmov)); in vmovlq()
3555 const IValueT Dm = mapQRegToDReg(encodeQRegister(OpQm, "Qm", Vmov)); in vmovlq()
3560 const IValueT VmovOpcode = B25 | B21 | B8 | B4; in vmovlq()
3579 const IValueT Dd = mapQRegToDReg(encodeQRegister(OpQd, "Qd", Vmov)); in vmovhq()
3580 const IValueT Dn = mapQRegToDReg(encodeQRegister(OpQn, "Qn", Vmov)); in vmovhq()
3581 const IValueT Dm = mapQRegToDReg(encodeQRegister(OpQm, "Qm", Vmov)); in vmovhq()
3586 const IValueT VmovOpcode = B25 | B21 | B8 | B4; in vmovhq()
3605 const IValueT Dd = mapQRegToDReg(encodeQRegister(OpQd, "Qd", Vmov)); in vmovhlq()
3606 const IValueT Dn = mapQRegToDReg(encodeQRegister(OpQn, "Qn", Vmov)); in vmovhlq()
3607 const IValueT Dm = mapQRegToDReg(encodeQRegister(OpQm, "Qm", Vmov)); in vmovhlq()
3612 const IValueT VmovOpcode = B25 | B21 | B8 | B4; in vmovhlq()
3631 const IValueT Dd = mapQRegToDReg(encodeQRegister(OpQd, "Qd", Vmov)); in vmovlhq()
3632 const IValueT Dn = mapQRegToDReg(encodeQRegister(OpQn, "Qn", Vmov)); in vmovlhq()
3633 const IValueT Dm = mapQRegToDReg(encodeQRegister(OpQm, "Qm", Vmov)); in vmovlhq()
3638 const IValueT VmovOpcode = B25 | B21 | B8 | B4; in vmovlhq()
3657 constexpr IValueT VnegOpcode = B24 | B23 | B21 | B20 | B16 | B9 | B8 | B7; in vnegqs()
3658 const IValueT Qd = encodeQRegister(OpQd, "Qd", Vneg); in vnegqs()
3659 constexpr IValueT Qn = 0; in vnegqs()
3660 const IValueT Qm = encodeQRegister(OpQm, "Qm", Vneg); in vnegqs()
3662 constexpr IValueT ElmtShift = 18; in vnegqs()
3663 const IValueT ElmtSize = encodeElmtType(ElmtTy); in vnegqs()
3677 constexpr IValueT VorrqOpcode = B21 | B8 | B4; in vorrq()
3690 IValueT Dd = encodeDRegister(OpDd, "Dd", Vstrd); in vstrd()
3692 IValueT Address; in vstrd()
3693 IValueT AddressEncoding = in vstrd()
3697 IValueT Encoding = B27 | B26 | B24 | B11 | B9 | B8 | in vstrd()
3715 IValueT Dd = mapQRegToDReg(encodeQRegister(OpQd, "Dd", Vstrd)); in vstrq()
3717 IValueT Address; in vstrq()
3718 IValueT AddressEncoding = in vstrq()
3722 IValueT Encoding = B27 | B26 | B24 | B11 | B9 | B8 | in vstrq()
3737 IValueT Sd = encodeSRegister(OpSd, "Sd", Vstrs); in vstrs()
3739 IValueT Address; in vstrs()
3740 IValueT AddressEncoding = in vstrs()
3744 IValueT Encoding = in vstrs()
3759 const IValueT Qd = encodeQRegister(OpQd, "Qd", Vst1qr); in vst1qr()
3760 const IValueT Dd = mapQRegToDReg(Qd); in vst1qr()
3761 IValueT Address; in vst1qr()
3765 const IValueT Rn = mask(Address, kRnShift, 4); in vst1qr()
3766 constexpr IValueT Rm = RegARM32::Reg_pc; in vst1qr()
3767 constexpr IValueT Opcode = B26; in vst1qr()
3768 constexpr IValueT Align = 0; // use default alignment. in vst1qr()
3790 const IValueT Qd = encodeQRegister(OpQd, "Qd", Vst1qr); in vst1()
3791 const IValueT Dd = mapQRegToDReg(Qd); in vst1()
3792 IValueT Address; in vst1()
3796 const IValueT Rn = mask(Address, kRnShift, 4); in vst1()
3797 constexpr IValueT Rm = RegARM32::Reg_pc; in vst1()
3798 constexpr IValueT Opcode = B26 | B23; in vst1()
3799 constexpr IValueT Align = 0; // use default alignment. in vst1()
3811 constexpr IValueT VsubsOpcode = B21 | B20 | B6; in vsubs()
3823 constexpr IValueT VsubdOpcode = B21 | B20 | B6; in vsubd()
3837 constexpr IValueT VqaddqiOpcode = B4; in vqaddqi()
3851 constexpr IValueT VqaddquOpcode = B24 | B4; in vqaddqu()
3865 constexpr IValueT VqsubqiOpcode = B9 | B4; in vqsubqi()
3879 constexpr IValueT VqsubquOpcode = B24 | B9 | B4; in vqsubqu()
3893 constexpr IValueT VsubqiOpcode = B24 | B11; in vsubqi()
3915 const IValueT Qd = encodeQRegister(OpQd, "Qd", Vqmovn); in vqmovn2()
3916 const IValueT Qm = encodeQRegister(OpQm, "Qm", Vqmovn); in vqmovn2()
3917 const IValueT Qn = encodeQRegister(OpQn, "Qn", Vqmovn); in vqmovn2()
3918 const IValueT Dd = mapQRegToDReg(Qd); in vqmovn2()
3919 const IValueT Dm = mapQRegToDReg(Qm); in vqmovn2()
3920 const IValueT Dn = mapQRegToDReg(Qn); in vqmovn2()
3922 IValueT VqmovnOpcode = B25 | B24 | B23 | B21 | B20 | B17 | B9 | in vqmovn2()
3925 constexpr IValueT ElmtShift = 18; in vqmovn2()
3944 const IValueT VmovOpcode = B25 | B21 | B8 | B4; in vqmovn2()
3958 constexpr IValueT VsubqfOpcode = B21 | B11 | B8; in vsubqf()
3962 void AssemblerARM32::emitVStackOp(CondARM32::Cond Cond, IValueT Opcode, in emitVStackOp()
3965 const IValueT BaseReg = getEncodedSRegNum(OpBaseReg); in emitVStackOp()
3966 const IValueT DLastBit = mask(BaseReg, 0, 1); // Last bit of base register. in emitVStackOp()
3967 const IValueT Rd = mask(BaseReg, 1, 4); // Top 4 bits of base register. in emitVStackOp()
3973 const IValueT Encoding = Opcode | (Cond << kConditionShift) | DLastBit | in emitVStackOp()
3988 constexpr IValueT VpopOpcode = in vpop()
4003 constexpr IValueT VpushOpcode = in vpush()
4018 constexpr IValueT VshlOpcode = B10 | B6; in vshlqi()
4033 constexpr IValueT VshlOpcode = B23 | B10 | B8 | B4; in vshlqc()
4049 const IValueT VshrOpcode = in vshrqc()
4065 constexpr IValueT VshlOpcode = B24 | B10 | B6; in vshlqu()
4076 IValueT Dd = encodeDRegister(OpDd, "Dd", Vsqrtd); in vsqrtd()
4077 IValueT Dm = encodeDRegister(OpDm, "Dm", Vsqrtd); in vsqrtd()
4078 constexpr IValueT VsqrtdOpcode = B23 | B21 | B20 | B16 | B7 | B6; in vsqrtd()
4079 constexpr IValueT D0 = 0; in vsqrtd()
4090 IValueT Sd = encodeSRegister(OpSd, "Sd", Vsqrts); in vsqrts()
4091 IValueT Sm = encodeSRegister(OpSm, "Sm", Vsqrts); in vsqrts()
4092 constexpr IValueT VsqrtsOpcode = B23 | B21 | B20 | B16 | B7 | B6; in vsqrts()
4093 constexpr IValueT S0 = 0; in vsqrts()