Lines Matching refs:x1
33 ldr x1, =GICC_BASE
52 ldr x1, =GICC_BASE_64K
74 switch_el x1, 1f, 100f, 100f /* skip if not in EL3 */
82 ldr x1, =0x00000010
98 ldr x1, =0x00000020
101 ldr x1, =0x00000020
108 ldr x1, =CCI_MN_RNF_NODEID_LIST
114 ldr x1, =0x00FF000C
117 ldr x1, =0x00FF000C
120 ldr x1, =0x00FF000C
124 ldr x1, =0x00FF000C
127 ldr x1, =0x00FF000C
130 ldr x1, =0x00FF000C
134 ldr x1, =0x00FF000C
137 ldr x1, =0x00FF000C
140 ldr x1, =0x00FF000C
144 ldr x1, =0x00FF000C
147 ldr x1, =0x00FF000C
150 ldr x1, =0x00FF000C
154 ldr x1, =0x00FF000C
157 ldr x1, =0x00FF000C
160 ldr x1, =0x00FF000C
164 ldr x1, =0x00FF000C
167 ldr x1, =0x00FF000C
170 ldr x1, =0x00FF000C
176 ldr x1, =SMMU_BASE
177 ldr w0, [x1, #0x10]
179 str w0, [x1, #0x10]
198 branch_if_master x0, x1, 2f
206 switch_el x1, 1f, 100f, 100f /* skip if not in EL3 */
210 ldr x1, =TZPCDECPROT_0_SET_BASE /* Decode Protection-0 Set Reg */
212 str w0, [x1]
243 mov x1, #0x8
244 add x1, x1, x14
246 ldr w0, [x1] /* Filter 0 Gate Keeper Register */
248 str w0, [x1]
250 mov x1, #0x110
251 add x1, x1, x14
253 ldr w0, [x1] /* Region-0 Attributes Register */
256 str w0, [x1]
258 mov x1, #0x114
259 add x1, x1, x14
261 ldr w0, [x1] /* Region-0 Access Register */
263 str w0, [x1]
282 switch_el x1, 1f, 100f, 100f /* skip if not in EL3 */
285 mrs x1, S3_1_c11_c0_2
288 bic x1, x1, x0
290 orr x1, x1, #0x2
292 orr x1, x1, #0x80
293 msr S3_1_c11_c0_2, x1
318 ldr x1, =(CONFIG_SYS_FSL_OCRAM_BASE + CONFIG_SYS_FSL_OCRAM_SIZE)
323 cmp x0, x1
342 ldr x1, =FSL_LSCH3_SVR
343 ldr w0, [x1]
352 mov x1, x0
361 cmp x2, x1 /* check status */
378 mov x1, x0
386 orr x2, x2, x1
461 ubfm x1, x0, #8, #15
463 orr x10, x2, x1, lsl #2 /* x10 has LPID */
469 lsl x1, x10, #6
472 add x11, x1, x0
485 mov x0, x1
494 mrs x1, sctlr_el2
496 mrs x1, sctlr_el1
498 tbz x1, #25, cpu_is_le
532 ubfm x1, x0, #8, #15
534 orr x10, x2, x1, lsl #2 /* x10 has LPID */
536 lsl x1, x10, #6
539 add x11, x1, x0