Lines Matching refs:cru

10 #include <dt-bindings/clock/rk3228-cru.h>
35 			resets = <&cru SRST_CORE0>;
42 			clocks = <&cru ARMCLK>;
49 			resets = <&cru SRST_CORE1>;
56 			resets = <&cru SRST_CORE2>;
63 			resets = <&cru SRST_CORE3>;
79 			clocks = <&cru ACLK_DMAC>;
133 		clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
148 		clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
161 		clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
178 		clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
192 		clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
206 		clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
222 		clocks = <&cru PCLK_I2C0>;
235 		clocks = <&cru PCLK_I2C1>;
248 		clocks = <&cru PCLK_I2C2>;
261 		clocks = <&cru PCLK_I2C3>;
271 		clocks = <&cru PCLK_PWM>;
282 		clocks = <&cru PCLK_PWM>;
293 		clocks = <&cru PCLK_PWM>;
304 		clocks = <&cru PCLK_PWM>;
315 		clocks = <&xin24m>, <&cru PCLK_TIMER>;
319 	cru: clock-controller@110e0000 {  label
321 		compatible = "rockchip,rk3228-cru";
326 		assigned-clocks = <&cru PLL_GPLL>;
374 		clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
376 		resets = <&cru SRST_TSADC>;
392 		clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
393 			 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
405 		clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
406 			 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
419 		clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
420 			 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
428 		resets = <&cru SRST_EMMC>;
448 		clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
449 			<&cru SCLK_MAC_TX>, <&cru SCLK_MAC_REF>,
450 			<&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>,
451 			<&cru PCLK_GMAC>;
456 		resets = <&cru SRST_GMAC>;
486 			clocks = <&cru PCLK_GPIO0>;
499 			clocks = <&cru PCLK_GPIO1>;
512 			clocks = <&cru PCLK_GPIO2>;
525 			clocks = <&cru PCLK_GPIO3>;
768 		rockchip,cru = <&cru>;