Lines Matching refs:cru
7 #include <dt-bindings/clock/rk3288-cru.h>
79 clocks = <&cru ARMCLK>;
80 resets = <&cru SRST_CORE0>;
86 resets = <&cru SRST_CORE1>;
92 resets = <&cru SRST_CORE2>;
98 resets = <&cru SRST_CORE3>;
115 clocks = <&cru ACLK_DMAC2>;
126 clocks = <&cru ACLK_DMAC1>;
138 clocks = <&cru ACLK_DMAC1>;
169 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
170 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
181 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
182 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
193 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
194 <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
205 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
206 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
219 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
226 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
241 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
256 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
276 clocks = <&cru PCLK_I2C1>;
289 clocks = <&cru PCLK_I2C3>;
302 clocks = <&cru PCLK_I2C4>;
315 clocks = <&cru PCLK_I2C5>;
327 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
341 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
355 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
368 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
382 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
396 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
398 resets = <&cru SRST_TSADC>;
413 clocks = <&cru SCLK_MAC>,
414 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
415 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
416 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
427 clocks = <&cru HCLK_USBHOST0>;
441 clocks = <&cru HCLK_USBHOST1>;
453 clocks = <&cru HCLK_OTG0>;
465 clocks = <&cru HCLK_HSIC>;
473 rockchip,cru = <&cru>;
483 clocks = <&cru PCLK_DDRUPCTL0>, <&cru PCLK_PUBL0>,
484 <&cru PCLK_DDRUPCTL1>, <&cru PCLK_PUBL1>,
485 <&cru ARMCLK>;
498 clocks = <&cru PCLK_I2C0>;
511 clocks = <&cru PCLK_I2C2>;
523 clocks = <&cru PCLK_PWM>;
535 clocks = <&cru PCLK_PWM>;
547 clocks = <&cru PCLK_PWM>;
559 clocks = <&cru PCLK_PWM>;
598 cru: clock-controller@ff760000 { label
599 compatible = "rockchip,rk3288-cru";
605 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
606 <&cru PLL_NPLL>, <&cru ACLK_CPU>,
607 <&cru HCLK_CPU>, <&cru PCLK_CPU>,
608 <&cru ACLK_PERI>, <&cru HCLK_PERI>,
609 <&cru PCLK_PERI>;
626 clocks = <&cru PCLK_WDT>;
636 clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>;
655 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
666 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
668 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
710 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
712 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
755 clocks = <&cru SCLK_EDP>, <&cru SCLK_EDP_24M>, <&cru PCLK_EDP_CTRL>;
758 resets = <&cru 111>;
785 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
807 clocks = <&cru PCLK_LVDS_PHY>;
835 clocks = <&cru PCLK_MIPI_DSI0>;
874 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
899 clocks = <&cru ACLK_GPU>;
953 clocks = <&cru SCLK_OTGPHY0>;
960 clocks = <&cru SCLK_OTGPHY1>;
967 clocks = <&cru SCLK_OTGPHY2>;
984 clocks = <&cru PCLK_GPIO0>;
997 clocks = <&cru PCLK_GPIO1>;
1010 clocks = <&cru PCLK_GPIO2>;
1023 clocks = <&cru PCLK_GPIO3>;
1036 clocks = <&cru PCLK_GPIO4>;
1049 clocks = <&cru PCLK_GPIO5>;
1062 clocks = <&cru PCLK_GPIO6>;
1075 clocks = <&cru PCLK_GPIO7>;
1088 clocks = <&cru PCLK_GPIO8>;
1534 clocks = <&cru ACLK_GPU>;
1539 clocks = <&cru ACLK_HEVC>,
1540 <&cru SCLK_HEVC_CABAC>,
1541 <&cru SCLK_HEVC_CORE>,
1542 <&cru HCLK_HEVC>;
1547 clocks = <&cru ACLK_IEP>,
1548 <&cru ACLK_ISP>,
1549 <&cru ACLK_RGA>,
1550 <&cru ACLK_VIP>,
1551 <&cru ACLK_VOP0>,
1552 <&cru ACLK_VOP1>,
1553 <&cru DCLK_VOP0>,
1554 <&cru DCLK_VOP1>,
1555 <&cru HCLK_IEP>,
1556 <&cru HCLK_ISP>,
1557 <&cru HCLK_RGA>,
1558 <&cru HCLK_VIP>,
1559 <&cru HCLK_VOP0>,
1560 <&cru HCLK_VOP1>,
1561 <&cru PCLK_EDP_CTRL>,
1562 <&cru PCLK_HDMI_CTRL>,
1563 <&cru PCLK_LVDS_PHY>,
1564 <&cru PCLK_MIPI_CSI>,
1565 <&cru PCLK_MIPI_DSI0>,
1566 <&cru PCLK_MIPI_DSI1>,
1567 <&cru SCLK_EDP_24M>,
1568 <&cru SCLK_EDP>,
1569 <&cru SCLK_HDMI_CEC>,
1570 <&cru SCLK_HDMI_HDCP>,
1571 <&cru SCLK_ISP_JPE>,
1572 <&cru SCLK_ISP>,
1573 <&cru SCLK_RGA>;
1578 clocks = <&cru ACLK_VCODEC>,
1579 <&cru HCLK_VCODEC>;