Lines Matching refs:cru
6 #include <dt-bindings/clock/rk3328-cru.h>
41 // clocks = <&cru ARMCLK>;
134 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
146 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
158 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
178 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
205 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
220 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
235 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
258 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
271 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
284 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
297 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
310 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
338 clocks = <&cru ACLK_DMAC>;
349 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
351 resets = <&cru SRST_SARADC_P>;
362 cru: clock-controller@ff440000 { label
363 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
369 <&cru DCLK_LCDC>, <&cru SCLK_PDM>,
370 <&cru SCLK_RTC32K>, <&cru SCLK_UART0>,
371 <&cru SCLK_UART1>, <&cru SCLK_UART2>,
372 <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
373 <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>,
374 <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
375 <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
376 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
377 <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
378 <&cru SCLK_SDIO>, <&cru SCLK_TSP>,
379 <&cru SCLK_WIFI>, <&cru ARMCLK>,
380 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
381 <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>,
382 <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
383 <&cru HCLK_PERI>, <&cru PCLK_PERI>,
384 <&cru ACLK_VIO_PRE>, <&cru HCLK_VIO_PRE>,
385 <&cru ACLK_RGA_PRE>, <&cru SCLK_RGA>,
386 <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
387 <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
388 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
389 <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
390 <&cru SCLK_EFUSE>, <&cru PCLK_DDR>,
391 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>,
392 <&cru SCLK_RTC32K>, <&cru SCLK_USB3OTG_SUSPEND>;
394 <&cru HDMIPHY>, <&cru PLL_APLL>,
395 <&cru PLL_GPLL>, <&xin24m>,
428 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
439 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
440 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
451 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
464 clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>,
465 <&cru SCLK_MAC2IO_TX>, <&cru SCLK_MAC2IO_REF>,
466 <&cru SCLK_MAC2IO_REFOUT>, <&cru ACLK_MAC2IO>,
467 <&cru PCLK_MAC2IO>;
472 resets = <&cru SRST_GMAC2IO_A>;
505 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
547 clocks = <&cru PCLK_GPIO0>;
560 clocks = <&cru PCLK_GPIO1>;
573 clocks = <&cru PCLK_GPIO2>;
586 clocks = <&cru PCLK_GPIO3>;