Lines Matching refs:cru
6 #include <dt-bindings/clock/rk3399-cru.h>
77 clocks = <&cru ARMCLKL>;
85 clocks = <&cru ARMCLKL>;
93 clocks = <&cru ARMCLKL>;
101 clocks = <&cru ARMCLKL>;
110 clocks = <&cru ARMCLKB>;
118 clocks = <&cru ARMCLKB>;
165 clocks = <&cru ACLK_DMAC0_PERILP>;
175 clocks = <&cru ACLK_DMAC1_PERILP>;
190 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
191 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
210 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
211 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>,
212 <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>,
213 <&cru SRST_A_PCIE>;
230 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
231 <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
232 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
233 <&cru PCLK_GMAC>;
239 resets = <&cru SRST_A_GMAC>;
251 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
252 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
256 resets = <&cru SRST_SDIO0>;
267 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
268 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
272 resets = <&cru SRST_SDMMC>;
283 assigned-clocks = <&cru SCLK_EMMC>;
286 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
300 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
314 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
328 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
342 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
430 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
432 resets = <&cru SRST_P_SARADC>;
440 assigned-clocks = <&cru SCLK_I2C1>;
442 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
455 assigned-clocks = <&cru SCLK_I2C2>;
457 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
470 assigned-clocks = <&cru SCLK_I2C3>;
472 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
485 assigned-clocks = <&cru SCLK_I2C5>;
487 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
500 assigned-clocks = <&cru SCLK_I2C6>;
502 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
515 assigned-clocks = <&cru SCLK_I2C7>;
517 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
530 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
543 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
556 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
570 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
583 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
596 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
609 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
622 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
635 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
718 assigned-clocks = <&cru SCLK_TSADC>;
720 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
722 resets = <&cru SRST_TSADC>;
879 clocks = <&cru ACLK_IEP>,
880 <&cru HCLK_IEP>;
885 clocks = <&cru ACLK_RGA>,
886 <&cru HCLK_RGA>;
892 clocks = <&cru ACLK_VCODEC>,
893 <&cru HCLK_VCODEC>;
898 clocks = <&cru ACLK_VDU>,
899 <&cru HCLK_VDU>;
907 clocks = <&cru ACLK_GPU>;
914 clocks = <&cru PCLK_EDP_CTRL>;
918 clocks = <&cru ACLK_EMMC>;
923 clocks = <&cru ACLK_GMAC>,
924 <&cru PCLK_GMAC>;
931 clocks = <&cru ACLK_PERIHP>;
939 clocks = <&cru HCLK_SDMMC>,
940 <&cru SCLK_SDMMC>;
946 clocks = <&cru HCLK_SDIO>;
951 clocks = <&cru ACLK_USB3>;
962 clocks = <&cru ACLK_HDCP>,
963 <&cru HCLK_HDCP>,
964 <&cru PCLK_HDCP>;
969 clocks = <&cru ACLK_ISP0>,
970 <&cru HCLK_ISP0>;
976 clocks = <&cru ACLK_ISP1>,
977 <&cru HCLK_ISP1>;
983 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
984 <&cru SCLK_UPHY0_TCPDPHY_REF>;
988 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
989 <&cru SCLK_UPHY1_TCPDPHY_REF>;
998 clocks = <&cru ACLK_VOP0>,
999 <&cru HCLK_VOP0>;
1005 clocks = <&cru ACLK_VOP1>,
1006 <&cru HCLK_VOP1>;
1143 clocks = <&cru PCLK_DDR_MON>;
1153 clocks = <&cru SCLK_DDRCLK>;
1170 clocks = <&cru PCLK_EFUSE1024NS>;
1208 cru: clock-controller@ff760000 { label
1210 compatible = "rockchip,rk3399-cru";
1216 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1217 <&cru PLL_NPLL>,
1218 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1219 <&cru PCLK_PERIHP>,
1220 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
1221 <&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
1222 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
1248 clocks = <&cru SCLK_USB2PHY0_REF>;
1275 clocks = <&cru SCLK_USB2PHY1_REF>;
1310 clocks = <&cru SCLK_PCIEPHY_REF>;
1313 resets = <&cru SRST_PCIEPHY>;
1322 clocks = <&cru PCLK_WDT>;
1330 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1341 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1356 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1370 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1384 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1409 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1411 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1434 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1437 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1464 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_SFR>, <&cru PLL_VPLL>, <&cru PCLK_VIO_GRF>;
1488 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>,
1489 <&cru SCLK_DPHY_TX0_CFG>;
1552 clocks = <&cru PCLK_GPIO2>;
1565 clocks = <&cru PCLK_GPIO3>;
1578 clocks = <&cru PCLK_GPIO4>;