Lines Matching refs:rcc
47 #include <dt-bindings/mfd/stm32f4-rcc.h>
81 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
90 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
110 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
119 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
139 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
148 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
168 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
176 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
196 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
205 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
220 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
229 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
245 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM12)>;
266 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM13)>;
281 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM14)>;
294 clocks = <&rcc 1 CLK_RTC>;
296 assigned-clocks = <&rcc 1 CLK_RTC>;
297 assigned-clock-parents = <&rcc 1 CLK_LSE>;
316 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART2)>;
324 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART3)>;
335 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART4)>;
343 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART5)>;
352 resets = <&rcc STM32F4_APB1_RESET(I2C1)>;
353 clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C1)>;
362 resets = <&rcc STM32F4_APB1_RESET(DAC)>;
363 clocks = <&rcc 0 STM32F4_APB1_CLOCK(DAC)>;
388 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART7)>;
396 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART8)>;
405 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM1)>;
426 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM8)>;
446 clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART1)>;
457 clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART6)>;
465 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
477 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
489 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC2)>;
501 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC3)>;
528 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM9)>;
549 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM10)>;
564 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM11)>;
582 clocks = <&rcc 0 171>;
595 resets = <&rcc STM32F4_APB2_RESET(LTDC)>;
596 clocks = <&rcc 1 CLK_LCD>;
604 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(CRC)>;
608 rcc: rcc@40023810 { label
611 compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
615 assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
630 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA1)>;
645 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2)>;
657 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(ETHMAC)>,
658 <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACTX)>,
659 <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACRX)>;
670 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(OTGHS)>;
679 clocks = <&rcc 0 39>;
688 resets = <&rcc STM32F4_AHB2_RESET(DCMI)>;
689 clocks = <&rcc 0 STM32F4_AHB2_CLOCK(DCMI)>;
702 clocks = <&rcc 0 STM32F4_AHB2_CLOCK(RNG)>;
709 clocks = <&rcc 1 SYSTICK>;