32 	{PERIPH_ID_UART0,	0xf,	0xf,	-1,	0,	0,	-1},
33 	{PERIPH_ID_UART1,	0xf,	0xf,	-1,	4,	4,	-1},
34 	{PERIPH_ID_UART2,	0xf,	0xf,	-1,	8,	8,	-1},
35 	{PERIPH_ID_UART3,	0xf,	0xf,	-1,	12,	12,	-1},
44 	{PERIPH_ID_SPI0,	0xf,	0xf,	0xff,	16,	0,	8},
45 	{PERIPH_ID_SPI1,	0xf,	0xf,	0xff,	20,	16,	24},
46 	{PERIPH_ID_SPI2,	0xf,	0xf,	0xff,	24,	0,	8},
47 	{PERIPH_ID_SDMMC0,	0xf,	0xf,	0xff,	0,	0,	8},
48 	{PERIPH_ID_SDMMC1,	0xf,	0xf,	0xff,	4,	16,	24},
49 	{PERIPH_ID_SDMMC2,	0xf,	0xf,	0xff,	8,	0,	8},
50 	{PERIPH_ID_SDMMC3,	0xf,	0xf,	0xff,	12,	16,	24},
51 	{PERIPH_ID_I2S0,	0xf,	0xf,	0xff,	0,	0,	4},
52 	{PERIPH_ID_I2S1,	0xf,	0xf,	0xff,	4,	12,	16},
53 	{PERIPH_ID_SPI3,	0xf,	0xf,	0xff,	0,	0,	4},
54 	{PERIPH_ID_SPI4,	0xf,	0xf,	0xff,	4,	12,	16},
55 	{PERIPH_ID_SDMMC4,	0xf,	0xf,	0xff,	16,	0,	8},
56 	{PERIPH_ID_PWM0,	0xf,	0xf,	-1,	24,	0,	-1},
57 	{PERIPH_ID_PWM1,	0xf,	0xf,	-1,	24,	0,	-1},
58 	{PERIPH_ID_PWM2,	0xf,	0xf,	-1,	24,	0,	-1},
59 	{PERIPH_ID_PWM3,	0xf,	0xf,	-1,	24,	0,	-1},
60 	{PERIPH_ID_PWM4,	0xf,	0xf,	-1,	24,	0,	-1},
67 	{PERIPH_ID_UART0,	0xf,	0xf,	-1,	4,	8,	-1},
68 	{PERIPH_ID_UART1,	0xf,	0xf,	-1,	8,	12,	-1},
69 	{PERIPH_ID_UART2,	0xf,	0xf,	-1,	12,	16,	-1},
70 	{PERIPH_ID_UART3,	0xf,	0xf,	-1,	16,	20,	-1},
79 	{PERIPH_ID_SPI0,	0xf,	0xf,	0xff,	20,	20,	8},
80 	{PERIPH_ID_SPI1,	0xf,	0xf,	0xff,	24,	24,	16},
81 	{PERIPH_ID_SPI2,	0xf,	0xf,	0xff,	28,	28,	24},
87 	{PERIPH_ID_I2S0,	0xf,	0xf,	0xff,	0,	0,	4},
88 	{PERIPH_ID_I2S1,	0xf,	0xf,	0xff,	4,	12,	16},
89 	{PERIPH_ID_SPI3,	0xf,	0xf,	0xff,	12,	16,	0},
90 	{PERIPH_ID_SPI4,	0xf,	0xf,	0xff,	16,	20,	8},
91 	{PERIPH_ID_PWM0,	0xf,	0xf,	-1,	24,	28,	-1},
92 	{PERIPH_ID_PWM1,	0xf,	0xf,	-1,	24,	28,	-1},
93 	{PERIPH_ID_PWM2,	0xf,	0xf,	-1,	24,	28,	-1},
94 	{PERIPH_ID_PWM3,	0xf,	0xf,	-1,	24,	28,	-1},
95 	{PERIPH_ID_PWM4,	0xf,	0xf,	-1,	24,	28,	-1},
649 		sel = (sel >> 24) & 0xf;  in exynos4_get_pwm_clk()
665 		ratio = ratio & 0xf;  in exynos4_get_pwm_clk()
710 	sel = (sel >> (dev_index << 2)) & 0xf;  in exynos4_get_uart_clk()
731 	ratio = (ratio >> (dev_index << 2)) & 0xf;  in exynos4_get_uart_clk()
756 	sel = (sel >> (dev_index << 2)) & 0xf;  in exynos4x12_get_uart_clk()
776 	ratio = (ratio >> (dev_index << 2)) & 0xf;  in exynos4x12_get_uart_clk()
792 	sel = (sel >> (dev_index << 2)) & 0xf;  in exynos4_get_mmc_clk()
825 	ratio = (ratio >> shift) & 0xf;  in exynos4_get_mmc_clk()
925 	sel = sel & 0xf;  in exynos4_get_lcd_clk()
946 	ratio = ratio & 0xf;  in exynos4_get_lcd_clk()
967 	sel = sel & 0xf;  in exynos5_get_lcd_clk()
988 	ratio = ratio & 0xf;  in exynos5_get_lcd_clk()
1022 	ratio = ratio & 0xf;  in exynos5420_get_lcd_clk()
1058 	ratio = readl(&clk->div_disp10) & 0xf;  in exynos5800_get_lcd_clk()
1088 	clrsetbits_le32(&clk->src_lcd0, 0xf, 0x6);  in exynos4_set_lcd_clk()
1112 	clrsetbits_le32(&clk->div_lcd0, 0xf, 0x1);  in exynos4_set_lcd_clk()
1140 	clrsetbits_le32(&clk->src_disp1_0, 0xf, 0x6);  in exynos5_set_lcd_clk()
1164 	clrsetbits_le32(&clk->div_disp1_0, 0xf, 0x0);  in exynos5_set_lcd_clk()
1189 	cfg &= ~(0xf << 0);  in exynos5420_set_lcd_clk()
1213 	clrsetbits_le32(&clk->div_disp10, 0xf << 0, 0x0 << 0);  in exynos5800_set_lcd_clk()
1229 	clrsetbits_le32(&clk->src_lcd0, 0xf << 12, 0x6 << 12);  in exynos4_set_mipi_clk()
1263 	clrsetbits_le32(&clk->div_lcd0, 0xf << 16, 0x1 << 16);  in exynos4_set_mipi_clk()
1503 	unsigned div_mask = 0xf, pre_div_mask = 0xff;  in exynos5420_set_spi_clk()
1570 	ratio &= 0xf;  in exynos4_get_i2c_clk()