Lines Matching refs:ddrmr
112 struct ddrmr_regs *ddrmr = (struct ddrmr_regs *)DDR_BASE_ADDR; in ddrmc_ctrl_init_ddr3() local
116 writel(DDRMC_CR00_DRAM_CLASS_DDR3, &ddrmr->cr[0]); in ddrmc_ctrl_init_ddr3()
117 writel(DDRMC_CR02_DRAM_TINIT(timings->tinit), &ddrmr->cr[2]); in ddrmc_ctrl_init_ddr3()
118 writel(DDRMC_CR10_TRST_PWRON(timings->trst_pwron), &ddrmr->cr[10]); in ddrmc_ctrl_init_ddr3()
120 writel(DDRMC_CR11_CKE_INACTIVE(timings->cke_inactive), &ddrmr->cr[11]); in ddrmc_ctrl_init_ddr3()
122 DDRMC_CR12_CASLAT_LIN(timings->caslat_lin), &ddrmr->cr[12]); in ddrmc_ctrl_init_ddr3()
126 &ddrmr->cr[13]); in ddrmc_ctrl_init_ddr3()
129 DDRMC_CR14_TRAS_MIN(timings->tras_min), &ddrmr->cr[14]); in ddrmc_ctrl_init_ddr3()
131 DDRMC_CR16_TRTP(timings->trtp), &ddrmr->cr[16]); in ddrmc_ctrl_init_ddr3()
133 DDRMC_CR17_TMOD(timings->tmod), &ddrmr->cr[17]); in ddrmc_ctrl_init_ddr3()
135 DDRMC_CR18_TCKE(timings->tcke), &ddrmr->cr[18]); in ddrmc_ctrl_init_ddr3()
137 writel(DDRMC_CR20_AP_EN, &ddrmr->cr[20]); in ddrmc_ctrl_init_ddr3()
140 &ddrmr->cr[21]); in ddrmc_ctrl_init_ddr3()
142 writel(DDRMC_CR22_TDAL(timings->tdal), &ddrmr->cr[22]); in ddrmc_ctrl_init_ddr3()
144 DDRMC_CR23_TDLL(timings->tdll), &ddrmr->cr[23]); in ddrmc_ctrl_init_ddr3()
145 writel(DDRMC_CR24_TRP_AB(timings->trp_ab), &ddrmr->cr[24]); in ddrmc_ctrl_init_ddr3()
147 writel(DDRMC_CR25_TREF_EN, &ddrmr->cr[25]); in ddrmc_ctrl_init_ddr3()
149 DDRMC_CR26_TRFC(timings->trfc), &ddrmr->cr[26]); in ddrmc_ctrl_init_ddr3()
150 writel(DDRMC_CR28_TREF_INT(timings->tref_int), &ddrmr->cr[28]); in ddrmc_ctrl_init_ddr3()
151 writel(DDRMC_CR29_TPDEX(timings->tpdex), &ddrmr->cr[29]); in ddrmc_ctrl_init_ddr3()
153 writel(DDRMC_CR30_TXPDLL(timings->txpdll), &ddrmr->cr[30]); in ddrmc_ctrl_init_ddr3()
155 DDRMC_CR31_TXSR(timings->txsr), &ddrmr->cr[31]); in ddrmc_ctrl_init_ddr3()
156 writel(DDRMC_CR33_EN_QK_SREF, &ddrmr->cr[33]); in ddrmc_ctrl_init_ddr3()
158 DDRMC_CR34_CKSRE(timings->cksre), &ddrmr->cr[34]); in ddrmc_ctrl_init_ddr3()
160 writel(DDRMC_CR38_FREQ_CHG_EN(timings->freq_chg_en), &ddrmr->cr[38]); in ddrmc_ctrl_init_ddr3()
162 DDRMC_CR39_FRQ_CH_DLLOFF(2), &ddrmr->cr[39]); in ddrmc_ctrl_init_ddr3()
164 writel(DDRMC_CR41_PHY_INI_STRT_INI_DIS, &ddrmr->cr[41]); in ddrmc_ctrl_init_ddr3()
166 DDRMC_CR48_MR0_DA_0(1056), &ddrmr->cr[48]); in ddrmc_ctrl_init_ddr3()
169 DDRMC_CR66_ZQINIT(timings->zqinit), &ddrmr->cr[66]); in ddrmc_ctrl_init_ddr3()
170 writel(DDRMC_CR67_ZQCS(timings->zqcs), &ddrmr->cr[67]); in ddrmc_ctrl_init_ddr3()
171 writel(DDRMC_CR69_ZQ_ON_SREF_EX(2), &ddrmr->cr[69]); in ddrmc_ctrl_init_ddr3()
173 writel(DDRMC_CR70_REF_PER_ZQ(timings->ref_per_zq), &ddrmr->cr[70]); in ddrmc_ctrl_init_ddr3()
174 writel(DDRMC_CR72_ZQCS_ROTATE(timings->zqcs_rotate), &ddrmr->cr[72]); in ddrmc_ctrl_init_ddr3()
178 DDRMC_CR73_ROW_DIFF(row_diff), &ddrmr->cr[73]); in ddrmc_ctrl_init_ddr3()
182 &ddrmr->cr[74]); in ddrmc_ctrl_init_ddr3()
184 DDRMC_CR75_PLEN, &ddrmr->cr[75]); in ddrmc_ctrl_init_ddr3()
186 DDRMC_CR76_W2R_SPLT_EN, &ddrmr->cr[76]); in ddrmc_ctrl_init_ddr3()
188 DDRMC_CR77_SWAP_EN, &ddrmr->cr[77]); in ddrmc_ctrl_init_ddr3()
190 DDRMC_CR78_BUR_ON_FLY_BIT(12), &ddrmr->cr[78]); in ddrmc_ctrl_init_ddr3()
191 writel(DDRMC_CR79_CTLUPD_AREF(0), &ddrmr->cr[79]); in ddrmc_ctrl_init_ddr3()
193 writel(DDRMC_CR82_INT_MASK, &ddrmr->cr[82]); in ddrmc_ctrl_init_ddr3()
197 &ddrmr->cr[87]); in ddrmc_ctrl_init_ddr3()
198 writel(DDRMC_CR88_TODTL_CMD(4), &ddrmr->cr[88]); in ddrmc_ctrl_init_ddr3()
199 writel(DDRMC_CR89_AODT_RWSMCS(2), &ddrmr->cr[89]); in ddrmc_ctrl_init_ddr3()
201 writel(DDRMC_CR91_R2W_SMCSDL(2), &ddrmr->cr[91]); in ddrmc_ctrl_init_ddr3()
203 DDRMC_CR96_WLDQSEN(timings->wldqsen), &ddrmr->cr[96]); in ddrmc_ctrl_init_ddr3()
210 &ddrmr->cr[cr_setting->cr_rnum]); in ddrmc_ctrl_init_ddr3()
218 &ddrmr->phy[phy_setting->phy_rnum]); in ddrmc_ctrl_init_ddr3()
227 &ddrmr->phy[phy_setting->phy_rnum]); in ddrmc_ctrl_init_ddr3()
232 writel(DDRMC_CR00_DRAM_CLASS_DDR3 | DDRMC_CR00_START, &ddrmr->cr[0]); in ddrmc_ctrl_init_ddr3()
234 while (!(readl(&ddrmr->cr[80]) && 0x100)) in ddrmc_ctrl_init_ddr3()