Lines Matching refs:ddr3_cfg
1223 const struct mx6_ddr3_cfg *ddr3_cfg) in mx6_ddr3_cfg() argument
1238 u16 mem_speed = ddr3_cfg->mem_speed; in mx6_ddr3_cfg()
1274 switch (ddr3_cfg->density) { in mx6_ddr3_cfg()
1303 if (ddr3_cfg->pagesz == 1) { in mx6_ddr3_cfg()
1314 if (ddr3_cfg->pagesz == 1) { in mx6_ddr3_cfg()
1334 trc = DIV_ROUND_UP(ddr3_cfg->trcmin, clkper / 10) - 1; in mx6_ddr3_cfg()
1335 tras = DIV_ROUND_UP(ddr3_cfg->trasmin, clkper / 10) - 1; in mx6_ddr3_cfg()
1336 tcl = DIV_ROUND_UP(ddr3_cfg->trcd, clkper / 10) - 3; in mx6_ddr3_cfg()
1337 trp = DIV_ROUND_UP(ddr3_cfg->trcd, clkper / 10) - 1; in mx6_ddr3_cfg()
1344 sysinfo->cs_density, ddr3_cfg->density); in mx6_ddr3_cfg()
1377 debug("SRT=%d\n", ddr3_cfg->SRT); in mx6_ddr3_cfg()
1452 coladdr = ddr3_cfg->coladdr; in mx6_ddr3_cfg()
1453 if (ddr3_cfg->coladdr == 8) /* 8-bit COL is 0x3 */ in mx6_ddr3_cfg()
1455 else if (ddr3_cfg->coladdr == 12) /* 12-bit COL is 0x4 */ in mx6_ddr3_cfg()
1457 mmdc0->mdctl = (ddr3_cfg->rowaddr - 11) << 24 | /* ROW */ in mx6_ddr3_cfg()
1475 val = (sysinfo->rtt_wr & 3) << 9 | (ddr3_cfg->SRT & 1) << 7 | in mx6_ddr3_cfg()