14 scg_p scg1_regs = (scg_p)SCG1_RBASE;  variable
22 		reg = readl(&scg1_regs->sosccsr);  in scg_src_get_rate()
28 		reg = readl(&scg1_regs->firccsr);  in scg_src_get_rate()
34 		reg = readl(&scg1_regs->sirccsr);  in scg_src_get_rate()
40 		reg = readl(&scg1_regs->rtccsr);  in scg_src_get_rate()
74 	reg = readl(&scg1_regs->sirccsr);  in scg_sircdiv_get_rate()
78 	reg = readl(&scg1_regs->sircdiv);  in scg_sircdiv_get_rate()
112 	reg = readl(&scg1_regs->firccsr);  in scg_fircdiv_get_rate()
116 	reg = readl(&scg1_regs->fircdiv);  in scg_fircdiv_get_rate()
150 	reg = readl(&scg1_regs->sosccsr);  in scg_soscdiv_get_rate()
154 	reg = readl(&scg1_regs->soscdiv);  in scg_soscdiv_get_rate()
200 	reg = readl(&scg1_regs->apllpfd);  in scg_apll_pfd_get_rate()
250 	reg = readl(&scg1_regs->spllpfd);  in scg_spll_pfd_get_rate()
270 	reg = readl(&scg1_regs->apllcfg);  in scg_apll_get_rate()
298 	reg = readl(&scg1_regs->spllcfg);  in scg_spll_get_rate()
333 	reg = readl(&scg1_regs->ddrccr);  in scg_ddr_get_rate()
341 		reg = readl(&scg1_regs->apllcfg);  in scg_ddr_get_rate()
358 	reg = readl(&scg1_regs->niccsr);  in scg_nic_get_rate()
433 	reg = readl(&scg1_regs->csr);  in scg_sys_get_rate()
480 		reg = readl(&scg1_regs->spllcsr);  in decode_pll()
485 		reg = readl(&scg1_regs->spllcfg);  in decode_pll()
501 		num = readl(&scg1_regs->spllnum);  in decode_pll()
502 		denom = readl(&scg1_regs->splldenom);  in decode_pll()
509 		reg = readl(&scg1_regs->apllcsr);  in decode_pll()
514 		reg = readl(&scg1_regs->apllcfg);  in decode_pll()
530 		num = readl(&scg1_regs->apllnum);  in decode_pll()
531 		denom = readl(&scg1_regs->aplldenom);  in decode_pll()
538 		reg = readl(&scg1_regs->upllcsr);  in decode_pll()
633 			addr = (u32)(&scg1_regs->spllpfd);  in scg_enable_pll_pfd()
635 			addr = (u32)(&scg1_regs->apllpfd);  in scg_enable_pll_pfd()
645 			addr = (u32)(&scg1_regs->spllpfd);  in scg_enable_pll_pfd()
647 			addr = (u32)(&scg1_regs->apllpfd);  in scg_enable_pll_pfd()
657 			addr = (u32)(&scg1_regs->spllpfd);  in scg_enable_pll_pfd()
659 			addr = (u32)(&scg1_regs->apllpfd);  in scg_enable_pll_pfd()
669 			addr = (u32)(&scg1_regs->spllpfd);  in scg_enable_pll_pfd()
671 			addr = (u32)(&scg1_regs->apllpfd);  in scg_enable_pll_pfd()
778 			if (readl(&scg1_regs->upllcsr) &  in scg_enable_usb_pll()
810 	rccr_reg_val = readl(&scg1_regs->rccr);  in scg_a7_rccr_init()
815 	writel(rccr_reg_val, &scg1_regs->rccr);  in scg_a7_rccr_init()
852 	val = readl(&scg1_regs->spllcsr);  in scg_a7_spll_init()
854 	writel(val, &scg1_regs->spllcsr);  in scg_a7_spll_init()
866 	val = readl(&scg1_regs->spllpfd);  in scg_a7_spll_init()
871 	writel(val, &scg1_regs->spllpfd);  in scg_a7_spll_init()
876 	writel(SCG1_SPLL_CFG_NUM_24M_OSC, &scg1_regs->spllcfg);  in scg_a7_spll_init()
879 	val = readl(&scg1_regs->spllcsr);  in scg_a7_spll_init()
881 	writel(val, &scg1_regs->spllcsr);  in scg_a7_spll_init()
884 	while (!(readl(&scg1_regs->spllcsr) & SCG_SPLL_CSR_SPLLVLD_MASK))  in scg_a7_spll_init()
888 	val = readl(&scg1_regs->spllpfd);  in scg_a7_spll_init()
891 	writel(val, &scg1_regs->spllpfd);  in scg_a7_spll_init()
894 	val = readl(&scg1_regs->spllpfd);  in scg_a7_spll_init()
896 	writel(val, &scg1_regs->spllpfd);  in scg_a7_spll_init()
899 	while (!(readl(&scg1_regs->spllpfd) & SCG_PLL_PFD0_VALID_MASK))  in scg_a7_spll_init()
917 	writel(SCG1_DDRCCR_CFG_NUM, &scg1_regs->ddrccr);  in scg_a7_ddrclk_init()
961 	val = readl(&scg1_regs->apllcsr);  in scg_a7_apll_init()
963 	writel(val, &scg1_regs->apllcsr);  in scg_a7_apll_init()
966 	val = readl(&scg1_regs->apllpfd);  in scg_a7_apll_init()
968 	writel(val, &scg1_regs->apllpfd);  in scg_a7_apll_init()
972 	writel(SCG1_APLL_CFG_NUM_24M_OSC, &scg1_regs->apllcfg);  in scg_a7_apll_init()
975 	val = readl(&scg1_regs->apllcsr);  in scg_a7_apll_init()
977 	writel(val, &scg1_regs->apllcsr);  in scg_a7_apll_init()
980 	while (!(readl(&scg1_regs->apllcsr) & SCG_APLL_CSR_APLLVLD_MASK))  in scg_a7_apll_init()
984 	val = readl(&scg1_regs->apllpfd);  in scg_a7_apll_init()
987 	writel(val, &scg1_regs->apllpfd);  in scg_a7_apll_init()
990 	val = readl(&scg1_regs->apllpfd);  in scg_a7_apll_init()
992 	writel(val, &scg1_regs->apllpfd);  in scg_a7_apll_init()
995 	while (!(readl(&scg1_regs->apllpfd) & SCG_PLL_PFD0_VALID_MASK))  in scg_a7_apll_init()
1010 	while (!(readl(&scg1_regs->firccsr) & SCG_FIRC_CSR_FIRCVLD_MASK))  in scg_a7_firc_init()
1016 			SCG1_FIRCDIV_DIV1_NUM), &scg1_regs->fircdiv);  in scg_a7_firc_init()
1038 	writel(SCG1_NICCCR_CFG_NUM, &scg1_regs->nicccr);  in scg_a7_nicclk_init()
1052 	while (!(readl(&scg1_regs->sosccsr) & SCG_SOSC_CSR_SOSCVLD_MASK))  in scg_a7_soscdiv_init()
1057 	       SCG1_SOSCDIV_DIV1_NUM), &scg1_regs->soscdiv);  in scg_a7_soscdiv_init()
1075 	rccr_reg_val = readl(&scg1_regs->rccr);  in scg_a7_sys_clk_sel()
1078 	writel(rccr_reg_val, &scg1_regs->rccr);  in scg_a7_sys_clk_sel()
1083 	debug("SCG Version: 0x%x\n", readl(&scg1_regs->verid));  in scg_a7_info()
1084 	debug("SCG Parameter: 0x%x\n", readl(&scg1_regs->param));  in scg_a7_info()
1085 	debug("SCG RCCR Value: 0x%x\n", readl(&scg1_regs->rccr));  in scg_a7_info()
1086 	debug("SCG Clock Status: 0x%x\n", readl(&scg1_regs->csr));  in scg_a7_info()