20 	u32 pll_cfg0, pll_cfg1, pllout;  in decode_frac_pll()  local
27 		pll_cfg0 = readl(&ana_pll->arm_pll_cfg0);  in decode_frac_pll()
41 	if (pll_cfg0 & FRAC_PLL_PD_MASK)  in decode_frac_pll()
45 	if ((pll_cfg0 & FRAC_PLL_CLKE_MASK) == 0)  in decode_frac_pll()
48 	pll_refclk_sel = pll_cfg0 & FRAC_PLL_REFCLK_SEL_MASK;  in decode_frac_pll()
59 	if (pll_cfg0 & FRAC_PLL_BYPASS_MASK)  in decode_frac_pll()
62 	divr_val = (pll_cfg0 & FRAC_PLL_REFCLK_DIV_VAL_MASK) >>  in decode_frac_pll()
64 	divq_val = pll_cfg0 & FRAC_PLL_OUTPUT_DIV_VAL_MASK;  in decode_frac_pll()
80 	u32 pll_cfg0, pll_cfg1, pll_cfg2;  in decode_sscg_pll()  local
98 		pll_cfg0 = readl(&ana_pll->sys_pll1_cfg0);  in decode_sscg_pll()
113 		pll_cfg0 = readl(&ana_pll->sys_pll2_cfg0);  in decode_sscg_pll()
120 		pll_cfg0 = readl(&ana_pll->sys_pll3_cfg0);  in decode_sscg_pll()
127 		pll_cfg0 = readl(&ana_pll->dram_pll_cfg0);  in decode_sscg_pll()
198 	if (pll_cfg0 & SSCG_PLL_PD_MASK)  in decode_sscg_pll()
202 	if ((pll_cfg0 & pll_clke) == 0)  in decode_sscg_pll()
208 	pll_refclk_sel = pll_cfg0 & SSCG_PLL_REFCLK_SEL_MASK;  in decode_sscg_pll()
220 	if ((pll_cfg0 & SSCG_PLL_BYPASS1_MASK) ||  in decode_sscg_pll()
221 	    (pll_cfg0 & SSCG_PLL_BYPASS2_MASK))  in decode_sscg_pll()
567 	void __iomem *pll_cfg0, __iomem *pll_cfg1;  in frac_pll_init()  local
573 		pll_cfg0 = &ana_pll->arm_pll_cfg0;  in frac_pll_init()
590 	setbits_le32(pll_cfg0, FRAC_PLL_BYPASS_MASK);  in frac_pll_init()
593 	writel(val_cfg0 | FRAC_PLL_BYPASS_MASK, pll_cfg0);  in frac_pll_init()
594 	val_cfg0 = readl(pll_cfg0);  in frac_pll_init()
596 	clrbits_le32(pll_cfg0, FRAC_PLL_BYPASS_MASK);  in frac_pll_init()
597 	ret = readl_poll_timeout(pll_cfg0, val_cfg0,  in frac_pll_init()
601 	clrbits_le32(pll_cfg0, FRAC_PLL_NEWDIV_VAL_MASK);  in frac_pll_init()
608 	void __iomem *pll_cfg0, __iomem *pll_cfg1, __iomem *pll_cfg2;  in sscg_pll_init()  local
615 		pll_cfg0 = &ana_pll->sys_pll1_cfg0;  in sscg_pll_init()
630 		pll_cfg0 = &ana_pll->sys_pll2_cfg0;  in sscg_pll_init()
645 		pll_cfg0 = &ana_pll->sys_pll3_cfg0;  in sscg_pll_init()
660 	setbits_le32(pll_cfg0, bypass1_mask | bypass2_mask);  in sscg_pll_init()
671 	ret = readl_poll_timeout(pll_cfg0, val, val & SSCG_PLL_LOCK_MASK, 1);  in sscg_pll_init()