Lines Matching refs:pll_clke
84 u32 pll_clke; in decode_sscg_pll() local
140 pll_clke = SSCG_PLL_DRAM_PLL_CLKE_MASK; in decode_sscg_pll()
144 pll_clke = SSCG_PLL_PLL3_CLKE_MASK; in decode_sscg_pll()
149 pll_clke = SSCG_PLL_CLKE_MASK; in decode_sscg_pll()
154 pll_clke = SSCG_PLL_DIV2_CLKE_MASK; in decode_sscg_pll()
159 pll_clke = SSCG_PLL_DIV3_CLKE_MASK; in decode_sscg_pll()
164 pll_clke = SSCG_PLL_DIV4_CLKE_MASK; in decode_sscg_pll()
169 pll_clke = SSCG_PLL_DIV5_CLKE_MASK; in decode_sscg_pll()
174 pll_clke = SSCG_PLL_DIV6_CLKE_MASK; in decode_sscg_pll()
179 pll_clke = SSCG_PLL_DIV8_CLKE_MASK; in decode_sscg_pll()
184 pll_clke = SSCG_PLL_DIV10_CLKE_MASK; in decode_sscg_pll()
189 pll_clke = SSCG_PLL_DIV20_CLKE_MASK; in decode_sscg_pll()
202 if ((pll_cfg0 & pll_clke) == 0) in decode_sscg_pll()
533 u32 pwdn_mask = 0, pll_clke = 0, bypass1 = 0, bypass2 = 0; in dram_pll_init() local
541 pll_clke = SSCG_PLL_DRAM_PLL_CLKE_MASK; in dram_pll_init()
552 setbits_le32(pll_control_reg, pll_clke); in dram_pll_init()