Lines Matching refs:__raw_readl
28 while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) in ddr3_init_ddrphy()
34 tmp = __raw_readl(base + KS2_DDRPHY_PGCR1_OFFSET); in ddr3_init_ddrphy()
44 tmp = __raw_readl(base + KS2_DDRPHY_DCR_OFFSET); in ddr3_init_ddrphy()
63 while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) & 0x1) != 0x1) in ddr3_init_ddrphy()
97 while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) & 0x1) != 0x1) in ddr3_init_ddrphy()
114 u32 value = __raw_readl(base + KS2_DDR3_MIDR_OFFSET); in ddr3_ecc_support_rmw()
133 data = __raw_readl(base + KS2_DDR3_ONE_BIT_ECC_ERR_CNT_OFFSET); in ddr3_ecc_config()
331 u32 value = __raw_readl(base + KS2_DDR3_ECC_INT_STATUS_OFFSET); in ddr3_check_ecc_int()
349 value = __raw_readl(base + KS2_DDR3_ONE_BIT_ECC_ERR_CNT_OFFSET); in ddr3_check_ecc_int()
352 value = __raw_readl(base + in ddr3_check_ecc_int()
392 tmp_a = __raw_readl(KS2_DDR3A_DDRPHYC + KS2_DDRPHY_PGSR0_OFFSET); in ddr3_err_reset_workaround()
393 tmp_b = __raw_readl(KS2_DDR3B_DDRPHYC + KS2_DDRPHY_PGSR0_OFFSET); in ddr3_err_reset_workaround()
411 tmp_a = __raw_readl(KS2_PSC_BASE + in ddr3_err_reset_workaround()
422 tmp_b = __raw_readl(KS2_PSC_BASE + in ddr3_err_reset_workaround()
432 tmp = __raw_readl(KS2_RSTCTRL); in ddr3_err_reset_workaround()
441 tmp = __raw_readl(KS2_RSTCTRL_RSCFG); in ddr3_err_reset_workaround()