24 void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg)  in ddr3_init_ddrphy()  argument
32 	__raw_writel(phy_cfg->pllcr, base + KS2_DDRPHY_PLLCR_OFFSET);  in ddr3_init_ddrphy()
35 	tmp &= ~(phy_cfg->pgcr1_mask);  in ddr3_init_ddrphy()
36 	tmp |= phy_cfg->pgcr1_val;  in ddr3_init_ddrphy()
39 	__raw_writel(phy_cfg->ptr0,   base + KS2_DDRPHY_PTR0_OFFSET);  in ddr3_init_ddrphy()
40 	__raw_writel(phy_cfg->ptr1,   base + KS2_DDRPHY_PTR1_OFFSET);  in ddr3_init_ddrphy()
41 	__raw_writel(phy_cfg->ptr3,  base + KS2_DDRPHY_PTR3_OFFSET);  in ddr3_init_ddrphy()
42 	__raw_writel(phy_cfg->ptr4,  base + KS2_DDRPHY_PTR4_OFFSET);  in ddr3_init_ddrphy()
45 	tmp &= ~(phy_cfg->dcr_mask);  in ddr3_init_ddrphy()
46 	tmp |= phy_cfg->dcr_val;  in ddr3_init_ddrphy()
49 	__raw_writel(phy_cfg->dtpr0, base + KS2_DDRPHY_DTPR0_OFFSET);  in ddr3_init_ddrphy()
50 	__raw_writel(phy_cfg->dtpr1, base + KS2_DDRPHY_DTPR1_OFFSET);  in ddr3_init_ddrphy()
51 	__raw_writel(phy_cfg->dtpr2, base + KS2_DDRPHY_DTPR2_OFFSET);  in ddr3_init_ddrphy()
52 	__raw_writel(phy_cfg->mr0,   base + KS2_DDRPHY_MR0_OFFSET);  in ddr3_init_ddrphy()
53 	__raw_writel(phy_cfg->mr1,   base + KS2_DDRPHY_MR1_OFFSET);  in ddr3_init_ddrphy()
54 	__raw_writel(phy_cfg->mr2,   base + KS2_DDRPHY_MR2_OFFSET);  in ddr3_init_ddrphy()
55 	__raw_writel(phy_cfg->dtcr,  base + KS2_DDRPHY_DTCR_OFFSET);  in ddr3_init_ddrphy()
56 	__raw_writel(phy_cfg->pgcr2, base + KS2_DDRPHY_PGCR2_OFFSET);  in ddr3_init_ddrphy()
58 	__raw_writel(phy_cfg->zq0cr1, base + KS2_DDRPHY_ZQ0CR1_OFFSET);  in ddr3_init_ddrphy()
59 	__raw_writel(phy_cfg->zq1cr1, base + KS2_DDRPHY_ZQ1CR1_OFFSET);  in ddr3_init_ddrphy()
60 	__raw_writel(phy_cfg->zq2cr1, base + KS2_DDRPHY_ZQ2CR1_OFFSET);  in ddr3_init_ddrphy()
62 	__raw_writel(phy_cfg->pir_v1, base + KS2_DDRPHY_PIR_OFFSET);  in ddr3_init_ddrphy()
68 				phy_cfg->datx8_2_mask,  in ddr3_init_ddrphy()
69 				phy_cfg->datx8_2_val);  in ddr3_init_ddrphy()
72 				phy_cfg->datx8_3_mask,  in ddr3_init_ddrphy()
73 				phy_cfg->datx8_3_val);  in ddr3_init_ddrphy()
76 				phy_cfg->datx8_4_mask,  in ddr3_init_ddrphy()
77 				phy_cfg->datx8_4_val);  in ddr3_init_ddrphy()
80 				phy_cfg->datx8_5_mask,  in ddr3_init_ddrphy()
81 				phy_cfg->datx8_5_val);  in ddr3_init_ddrphy()
84 				phy_cfg->datx8_6_mask,  in ddr3_init_ddrphy()
85 				phy_cfg->datx8_6_val);  in ddr3_init_ddrphy()
88 				phy_cfg->datx8_7_mask,  in ddr3_init_ddrphy()
89 				phy_cfg->datx8_7_val);  in ddr3_init_ddrphy()
92 				phy_cfg->datx8_8_mask,  in ddr3_init_ddrphy()
93 				phy_cfg->datx8_8_val);  in ddr3_init_ddrphy()
96 	__raw_writel(phy_cfg->pir_v2, base + KS2_DDRPHY_PIR_OFFSET);  in ddr3_init_ddrphy()