Lines Matching refs:fn
14 #define CPU_32_PORT(fn, pfx, sfx) \ argument
15 PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
16 PORT_10(fn, pfx##2, sfx), PORT_1(fn, pfx##30, sfx), \
17 PORT_1(fn, pfx##31, sfx)
19 #define CPU_32_PORT2(fn, pfx, sfx) \ argument
20 PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
21 PORT_10(fn, pfx##2, sfx)
24 #define CPU_32_PORT1(fn, pfx, sfx) \ argument
25 PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
26 PORT_10(fn, pfx##2, sfx) \
28 #define CPU_ALL_PORT(fn, pfx, sfx) \ argument
29 CPU_32_PORT(fn, pfx##_0_, sfx), \
30 CPU_32_PORT1(fn, pfx##_1_, sfx), \
31 CPU_32_PORT2(fn, pfx##_2_, sfx), \
32 CPU_32_PORT(fn, pfx##_3_, sfx), \
33 CPU_32_PORT(fn, pfx##_4_, sfx), \
34 CPU_32_PORT(fn, pfx##_5_, sfx)
37 #define CPU_32_PORT1(fn, pfx, sfx) \ argument
38 PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
39 PORT_1(fn, pfx##20, sfx), PORT_1(fn, pfx##21, sfx), \
40 PORT_1(fn, pfx##22, sfx), PORT_1(fn, pfx##23, sfx), \
41 PORT_1(fn, pfx##24, sfx), PORT_1(fn, pfx##25, sfx)
48 #define CPU_ALL_PORT(fn, pfx, sfx) \ argument
49 CPU_32_PORT(fn, pfx##_0_, sfx), \
50 CPU_32_PORT1(fn, pfx##_1_, sfx), \
51 CPU_32_PORT(fn, pfx##_2_, sfx), \
52 CPU_32_PORT(fn, pfx##_3_, sfx), \
53 CPU_32_PORT(fn, pfx##_4_, sfx), \
54 CPU_32_PORT(fn, pfx##_5_, sfx), \
55 CPU_32_PORT(fn, pfx##_6_, sfx), \
56 CPU_32_PORT1(fn, pfx##_7_, sfx)
64 #define CPU_32_PORT0_28(fn, pfx, sfx) \ argument
65 PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
66 PORT_1(fn, pfx##20, sfx), PORT_1(fn, pfx##21, sfx), \
67 PORT_1(fn, pfx##22, sfx), PORT_1(fn, pfx##23, sfx), \
68 PORT_1(fn, pfx##24, sfx), PORT_1(fn, pfx##25, sfx), \
69 PORT_1(fn, pfx##26, sfx), PORT_1(fn, pfx##27, sfx), \
70 PORT_1(fn, pfx##28, sfx)
72 #define CPU_32_PORT0_22(fn, pfx, sfx) \ argument
73 PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
74 PORT_1(fn, pfx##20, sfx), PORT_1(fn, pfx##21, sfx), \
75 PORT_1(fn, pfx##22, sfx)
77 #define CPU_32_PORT0_27(fn, pfx, sfx) \ argument
78 PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
79 PORT_1(fn, pfx##20, sfx), PORT_1(fn, pfx##21, sfx), \
80 PORT_1(fn, pfx##22, sfx), PORT_1(fn, pfx##23, sfx), \
81 PORT_1(fn, pfx##24, sfx), PORT_1(fn, pfx##25, sfx), \
82 PORT_1(fn, pfx##26, sfx), PORT_1(fn, pfx##27, sfx)
84 #define CPU_32_PORT0_16(fn, pfx, sfx) \ argument
85 PORT_10(fn, pfx, sfx), \
86 PORT_1(fn, pfx##10, sfx),PORT_1(fn, pfx##11, sfx), \
87 PORT_1(fn, pfx##12, sfx), PORT_1(fn, pfx##13, sfx), \
88 PORT_1(fn, pfx##14, sfx), PORT_1(fn, pfx##15, sfx), \
89 PORT_1(fn, pfx##16, sfx)
91 #define CPU_ALL_PORT(fn, pfx, sfx) \ argument
92 CPU_32_PORT0_28(fn, pfx##_0_, sfx), \
93 CPU_32_PORT0_22(fn, pfx##_1_, sfx), \
94 CPU_32_PORT(fn, pfx##_2_, sfx), \
95 CPU_32_PORT0_27(fn, pfx##_3_, sfx), \
96 CPU_32_PORT0_16(fn, pfx##_4_, sfx), \
97 CPU_32_PORT0_16(fn, pfx##_5_, sfx), \
98 CPU_32_PORT0_16(fn, pfx##_6_, sfx), \
99 CPU_32_PORT0_16(fn, pfx##_7_, sfx), \
100 CPU_32_PORT0_16(fn, pfx##_8_, sfx), \
101 CPU_32_PORT0_16(fn, pfx##_9_, sfx), \
102 CPU_32_PORT(fn, pfx##_10_, sfx), \
103 CPU_32_PORT2(fn, pfx##_11_, sfx)
120 #define PORT_10_REV(fn, pfx, sfx) \ argument
121 PORT_1(fn, pfx##9, sfx), PORT_1(fn, pfx##8, sfx), \
122 PORT_1(fn, pfx##7, sfx), PORT_1(fn, pfx##6, sfx), \
123 PORT_1(fn, pfx##5, sfx), PORT_1(fn, pfx##4, sfx), \
124 PORT_1(fn, pfx##3, sfx), PORT_1(fn, pfx##2, sfx), \
125 PORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx)
127 #define CPU_32_PORT_REV(fn, pfx, sfx) \ argument
128 PORT_1(fn, pfx##31, sfx), PORT_1(fn, pfx##30, sfx), \
129 PORT_10_REV(fn, pfx##2, sfx), PORT_10_REV(fn, pfx##1, sfx), \
130 PORT_10_REV(fn, pfx, sfx)
135 #define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn) argument
136 #define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \ argument
137 FN_##ipsr, FN_##fn)