Lines Matching full:default
4 default 0xa2
79 default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
80 default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
81 default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
82 default "dbm-soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
83 default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
84 default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
85 default "de10-nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
86 default "is1" if TARGET_SOCFPGA_IS1
87 default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
88 default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
89 default "sr1500" if TARGET_SOCFPGA_SR1500
90 default "vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
93 default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
94 default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK
95 default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
96 default "devboards" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
97 default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
98 default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
99 default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
100 default "terasic" if TARGET_SOCFPGA_TERASIC_DE1_SOC
101 default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_NANO
102 default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
105 default "socfpga"
108 default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
109 default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
110 default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
111 default "socfpga_dbm_soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
112 default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
113 default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
114 default "socfpga_de10_nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
115 default "socfpga_is1" if TARGET_SOCFPGA_IS1
116 default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
117 default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
118 default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
119 default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA