106 	       &clock_manager_base->main_pll.vco);  in cm_basic_init()
109 	       &clock_manager_base->per_pll.vco);  in cm_basic_init()
112 	       &clock_manager_base->sdr_pll.vco);  in cm_basic_init()
127 	readl(&clock_manager_base->main_pll.vco);  in cm_basic_init()
128 	readl(&clock_manager_base->per_pll.vco);  in cm_basic_init()
129 	readl(&clock_manager_base->sdr_pll.vco);  in cm_basic_init()
136 	writel(cfg->main_vco_base, &clock_manager_base->main_pll.vco);  in cm_basic_init()
137 	writel(cfg->peri_vco_base, &clock_manager_base->per_pll.vco);  in cm_basic_init()
138 	writel(cfg->sdram_vco_base, &clock_manager_base->sdr_pll.vco);  in cm_basic_init()
193 	       &clock_manager_base->main_pll.vco);  in cm_basic_init()
197 	       &clock_manager_base->per_pll.vco);  in cm_basic_init()
201 	       &clock_manager_base->sdr_pll.vco);  in cm_basic_init()
234 	u32 mainvco = readl(&clock_manager_base->main_pll.vco);  in cm_basic_init()
238 	       &clock_manager_base->main_pll.vco);  in cm_basic_init()
240 	u32 periphvco = readl(&clock_manager_base->per_pll.vco);  in cm_basic_init()
244 	       &clock_manager_base->per_pll.vco);  in cm_basic_init()
249 		&clock_manager_base->sdr_pll.vco);  in cm_basic_init()
253 	       &clock_manager_base->main_pll.vco);  in cm_basic_init()
257 	       &clock_manager_base->per_pll.vco);  in cm_basic_init()
261 	       &clock_manager_base->sdr_pll.vco);  in cm_basic_init()
323 	reg = readl(&clock_manager_base->main_pll.vco);  in cm_get_main_vco_clk_hz()
338 	reg = readl(&clock_manager_base->per_pll.vco);  in cm_get_per_vco_clk_hz()
349 	reg = readl(&clock_manager_base->per_pll.vco);  in cm_get_per_vco_clk_hz()
377 	reg = readl(&clock_manager_base->sdr_pll.vco);  in cm_get_sdram_clk_hz()
388 	reg = readl(&clock_manager_base->sdr_pll.vco);  in cm_get_sdram_clk_hz()