21 	struct sunxi_ccm_reg * const ccm =  in clock_init_safe()  local
29 	       &ccm->cpu_ahb_apb0_cfg);  in clock_init_safe()
30 	writel(PLL1_CFG_DEFAULT, &ccm->pll1_cfg);  in clock_init_safe()
36 	       &ccm->cpu_ahb_apb0_cfg);  in clock_init_safe()
38 	setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_DMA);  in clock_init_safe()
40 	writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);  in clock_init_safe()
42 	setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_SATA);  in clock_init_safe()
43 	setbits_le32(&ccm->pll6_cfg, 0x1 << CCM_PLL6_CTRL_SATA_EN_SHIFT);  in clock_init_safe()
50 	struct sunxi_ccm_reg *const ccm =  in clock_init_uart()  local
57 	       &ccm->apb1_clk_div_cfg);  in clock_init_uart()
60 	setbits_le32(&ccm->apb1_gate,  in clock_init_uart()
66 	struct sunxi_ccm_reg *const ccm =  in clock_twi_onoff()  local
71 		setbits_le32(&ccm->apb1_gate,  in clock_twi_onoff()
74 		clrbits_le32(&ccm->apb1_gate,  in clock_twi_onoff()
122 	struct sunxi_ccm_reg * const ccm =  in clock_set_pll1()  local
158 	       &ccm->cpu_ahb_apb0_cfg);  in clock_set_pll1()
166 	       &ccm->cpu_ahb_apb0_cfg);  in clock_set_pll1()
169 	writel(pll1_para[i].pll1_cfg, &ccm->pll1_cfg);  in clock_set_pll1()
177 	       &ccm->cpu_ahb_apb0_cfg);  in clock_set_pll1()
184 	struct sunxi_ccm_reg * const ccm =  in clock_set_pll3()  local
188 		clrbits_le32(&ccm->pll3_cfg, CCM_PLL3_CTRL_EN);  in clock_set_pll3()
194 	       CCM_PLL3_CTRL_M(clk / 3000000), &ccm->pll3_cfg);  in clock_set_pll3()
199 	struct sunxi_ccm_reg *const ccm =  in clock_get_pll3()  local
201 	uint32_t rval = readl(&ccm->pll3_cfg);  in clock_get_pll3()
208 	struct sunxi_ccm_reg *const ccm =  in clock_get_pll5p()  local
210 	uint32_t rval = readl(&ccm->pll5_cfg);  in clock_get_pll5p()
219 	struct sunxi_ccm_reg *const ccm =  in clock_get_pll6()  local
221 	uint32_t rval = readl(&ccm->pll6_cfg);  in clock_get_pll6()