21 	struct sunxi_ccm_reg * const ccm =  in clock_init_safe()  local
39 	writel(GENMASK(12, 0), &ccm->pll_lock_ctrl);  in clock_init_safe()
44 	writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);  in clock_init_safe()
45 	while (!(readl(&ccm->pll6_cfg) & CCM_PLL6_CTRL_LOCK))  in clock_init_safe()
48 	writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div);  in clock_init_safe()
50 	writel(MBUS_CLK_DEFAULT, &ccm->mbus0_clk_cfg);  in clock_init_safe()
52 		writel(MBUS_CLK_DEFAULT, &ccm->mbus1_clk_cfg);  in clock_init_safe()
55 	setbits_le32(&ccm->sata_pll_cfg, CCM_SATA_PLL_DEFAULT);  in clock_init_safe()
56 	setbits_le32(&ccm->ahb_reset0_cfg, 0x1 << AHB_GATE_OFFSET_SATA);  in clock_init_safe()
57 	setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_SATA);  in clock_init_safe()
58 	setbits_le32(&ccm->sata_clk_cfg, CCM_SATA_CTRL_ENABLE);  in clock_init_safe()
66 	struct sunxi_ccm_reg * const ccm =  in clock_init_sec()  local
71 	setbits_le32(&ccm->ccu_sec_switch,  in clock_init_sec()
85 	struct sunxi_ccm_reg *const ccm =  in clock_init_uart()  local
92 	       &ccm->apb2_div);  in clock_init_uart()
95 	setbits_le32(&ccm->apb2_gate,  in clock_init_uart()
100 	setbits_le32(&ccm->apb2_reset_cfg,  in clock_init_uart()
112 	struct sunxi_ccm_reg * const ccm =  in clock_set_pll1()  local
129 	       &ccm->cpu_axi_cfg);  in clock_set_pll1()
137 	       CCM_PLL1_CTRL_K(k) | CCM_PLL1_CTRL_M(m), &ccm->pll1_cfg);  in clock_set_pll1()
144 	       &ccm->cpu_axi_cfg);  in clock_set_pll1()
150 	struct sunxi_ccm_reg * const ccm =  in clock_set_pll3()  local
155 		clrbits_le32(&ccm->pll3_cfg, CCM_PLL3_CTRL_EN);  in clock_set_pll3()
162 	       &ccm->pll3_cfg);  in clock_set_pll3()
168 	struct sunxi_ccm_reg * const ccm =  in clock_set_pll3_factors()  local
174 	       &ccm->pll3_cfg);  in clock_set_pll3_factors()
176 	while (!(readl(&ccm->pll3_cfg) & CCM_PLL3_CTRL_LOCK))  in clock_set_pll3_factors()
183 	struct sunxi_ccm_reg * const ccm =  in clock_set_pll5()  local
189 	clrsetbits_le32(&ccm->pll5_tuning_cfg, CCM_PLL5_TUN_LOCK_TIME_MASK |  in clock_set_pll5()
195 		writel(CCM_PLL5_PATTERN, &ccm->pll5_pattern_cfg);  in clock_set_pll5()
207 	       CCM_PLL5_CTRL_K(k) | CCM_PLL5_CTRL_M(m), &ccm->pll5_cfg);  in clock_set_pll5()
215 	struct sunxi_ccm_reg * const ccm =  in clock_set_mipi_pll()  local
249 	       CCM_MIPI_PLL_CTRL_M(best_m), &ccm->mipi_pll_cfg);  in clock_set_mipi_pll()
256 	struct sunxi_ccm_reg * const ccm =  in clock_set_pll10()  local
261 		clrbits_le32(&ccm->pll10_cfg, CCM_PLL10_CTRL_EN);  in clock_set_pll10()
268 	       &ccm->pll10_cfg);  in clock_set_pll10()
270 	while (!(readl(&ccm->pll10_cfg) & CCM_PLL10_CTRL_LOCK))  in clock_set_pll10()
280 	struct sunxi_ccm_reg * const ccm =  in clock_set_pll11()  local
284 		writel(CCM_PLL11_PATTERN, &ccm->pll11_pattern_cfg0);  in clock_set_pll11()
288 	       CCM_PLL11_CTRL_N(clk / 24000000), &ccm->pll11_cfg);  in clock_set_pll11()
290 	while (readl(&ccm->pll11_cfg) & CCM_PLL11_CTRL_UPD)  in clock_set_pll11()
297 	struct sunxi_ccm_reg *const ccm =  in clock_get_pll3()  local
299 	uint32_t rval = readl(&ccm->pll3_cfg);  in clock_get_pll3()
309 	struct sunxi_ccm_reg *const ccm =  in clock_get_pll6()  local
311 	uint32_t rval = readl(&ccm->pll6_cfg);  in clock_get_pll6()
319 	struct sunxi_ccm_reg *const ccm =  in clock_get_mipi_pll()  local
321 	uint32_t rval = readl(&ccm->mipi_pll_cfg);  in clock_get_mipi_pll()