60 	struct sunxi_dram_reg *dram =  in mctl_ddr3_reset()  local
73 		setbits_le32(&dram->mcr, DRAM_MCR_RESET);  in mctl_ddr3_reset()
75 		clrbits_le32(&dram->mcr, DRAM_MCR_RESET);  in mctl_ddr3_reset()
79 		clrbits_le32(&dram->mcr, DRAM_MCR_RESET);  in mctl_ddr3_reset()
81 		setbits_le32(&dram->mcr, DRAM_MCR_RESET);  in mctl_ddr3_reset()
100 	struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;  in mctl_set_drive()  local
103 	clrsetbits_le32(&dram->mcr, DRAM_MCR_MODE_NORM(0x3) | (0x3 << 28),  in mctl_set_drive()
105 	clrsetbits_le32(&dram->mcr, DRAM_MCR_MODE_NORM(0x3),  in mctl_set_drive()
113 	struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;  in mctl_itm_disable()  local
115 	clrsetbits_le32(&dram->ccr, DRAM_CCR_INIT, DRAM_CCR_ITM_OFF);  in mctl_itm_disable()
120 	struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;  in mctl_itm_enable()  local
122 	clrbits_le32(&dram->ccr, DRAM_CCR_ITM_OFF);  in mctl_itm_enable()
135 	struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;  in mctl_enable_dll0()  local
137 	clrsetbits_le32(&dram->dllcr[0], 0x3f << 6,  in mctl_enable_dll0()
139 	clrsetbits_le32(&dram->dllcr[0], DRAM_DLLCR_NRESET, DRAM_DLLCR_DISABLE);  in mctl_enable_dll0()
142 	clrbits_le32(&dram->dllcr[0], DRAM_DLLCR_NRESET | DRAM_DLLCR_DISABLE);  in mctl_enable_dll0()
145 	clrsetbits_le32(&dram->dllcr[0], DRAM_DLLCR_DISABLE, DRAM_DLLCR_NRESET);  in mctl_enable_dll0()
152 	struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;  in mctl_get_number_of_lanes()  local
153 	if ((readl(&dram->dcr) & DRAM_DCR_BUS_WIDTH_MASK) ==  in mctl_get_number_of_lanes()
165 	struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;  in mctl_enable_dllx()  local
171 		clrsetbits_le32(&dram->dllcr[i], 0xf << 14,  in mctl_enable_dllx()
173 		clrsetbits_le32(&dram->dllcr[i], DRAM_DLLCR_NRESET,  in mctl_enable_dllx()
180 		clrbits_le32(&dram->dllcr[i], DRAM_DLLCR_NRESET |  in mctl_enable_dllx()
185 		clrsetbits_le32(&dram->dllcr[i], DRAM_DLLCR_DISABLE,  in mctl_enable_dllx()
230 	struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;  in mctl_configure_hostport()  local
234 		writel(hpcr_value[i], &dram->hpcr[i]);  in mctl_configure_hostport()
367 	struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;  in mctl_set_dqs_gating_delay()  local
370 	u32 slr = readl(rank == 0 ? &dram->rslr0 : &dram->rslr1);  in mctl_set_dqs_gating_delay()
372 	u32 dgr = readl(rank == 0 ? &dram->rdgr0 : &dram->rdgr1);  in mctl_set_dqs_gating_delay()
380 	writel(slr, rank == 0 ? &dram->rslr0 : &dram->rslr1);  in mctl_set_dqs_gating_delay()
381 	writel(dgr, rank == 0 ? &dram->rdgr0 : &dram->rdgr1);  in mctl_set_dqs_gating_delay()
386 	struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;  in dramc_scan_readpipe()  local
390 	clrbits_le32(&dram->csr, DRAM_CSR_FAILED);  in dramc_scan_readpipe()
391 	setbits_le32(&dram->ccr, DRAM_CCR_DATA_TRAINING);  in dramc_scan_readpipe()
394 	await_bits_clear(&dram->ccr, DRAM_CCR_DATA_TRAINING);  in dramc_scan_readpipe()
397 	reg_val = readl(&dram->csr);  in dramc_scan_readpipe()
407 	struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;  in dramc_clock_output_en()  local
410 		setbits_le32(&dram->mcr, DRAM_MCR_DCLK_OUT);  in dramc_clock_output_en()
412 		clrbits_le32(&dram->mcr, DRAM_MCR_DCLK_OUT);  in dramc_clock_output_en()
431 	struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;  in dramc_set_autorefresh_cycle()  local
437 	writel(DRAM_DRR_TREFI(tREFI) | DRAM_DRR_TRFC(tRFC), &dram->drr);  in dramc_set_autorefresh_cycle()
469 	struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;  in mctl_disable_power_save()  local
470 	writel(0x16510000, &dram->ppwrsctl);  in mctl_disable_power_save()
482 	struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;  in mctl_set_cke_delay()  local
490 	setbits_le32(&dram->idcr, 0x1ffff);  in mctl_set_cke_delay()
502 	struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;  in mctl_ddr3_initialize()  local
503 	setbits_le32(&dram->ccr, DRAM_CCR_INIT);  in mctl_ddr3_initialize()
504 	await_bits_clear(&dram->ccr, DRAM_CCR_INIT);  in mctl_ddr3_initialize()
512 	struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;  in mctl_set_impedance()  local
521 	await_bits_set(&dram->zqsr, DRAM_ZQSR_ZDONE);  in mctl_set_impedance()
535 	writel((1 << 24) | (1 << 1), &dram->zqcr1);  in mctl_set_impedance()
539 	clrbits_le32(&dram->zqcr0, DRAM_ZQCR0_ZCAL);  in mctl_set_impedance()
544 		writel(reg_val, &dram->zqcr0);  in mctl_set_impedance()
549 		writel(reg_val, &dram->zqcr0);  in mctl_set_impedance()
551 		await_bits_set(&dram->zqsr, DRAM_ZQSR_ZDONE);  in mctl_set_impedance()
555 	clrbits_le32(&dram->zqcr0, DRAM_ZQCR0_ZCAL);  in mctl_set_impedance()
558 	writel(DRAM_IOCR_ODT_EN, &dram->iocr);  in mctl_set_impedance()
563 	struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;  in dramc_init_helper()  local
588 	writel(DRAM_CSEL_MAGIC, &dram->csel);  in dramc_init_helper()
618 	writel(reg_val, &dram->dcr);  in dramc_init_helper()
630 	await_bits_clear(&dram->ccr, DRAM_CCR_INIT);  in dramc_init_helper()
638 	writel(para->tpr0, &dram->tpr0);  in dramc_init_helper()
639 	writel(para->tpr1, &dram->tpr1);  in dramc_init_helper()
640 	writel(para->tpr2, &dram->tpr2);  in dramc_init_helper()
648 	writel(reg_val, &dram->mr);  in dramc_init_helper()
650 	writel(para->emr1, &dram->emr);  in dramc_init_helper()
651 	writel(para->emr2, &dram->emr2);  in dramc_init_helper()
652 	writel(para->emr3, &dram->emr3);  in dramc_init_helper()
655 	clrsetbits_le32(&dram->ccr, DRAM_CCR_DQS_DRIFT_COMP, DRAM_CCR_DQS_GATE);  in dramc_init_helper()
660 		setbits_le32(&dram->ccr, DRAM_CCR_COMMAND_RATE_1T);  in dramc_init_helper()
680 		clrbits_le32(&dram->ccr, DRAM_CCR_DQS_GATE);  in dramc_init_helper()
682 		setbits_le32(&dram->ccr, DRAM_CCR_DQS_GATE);  in dramc_init_helper()