31 static void mctl_set_cr(struct dram_para *para)  in mctl_set_cr()  argument
36 	writel(MCTL_CR_CS1_CONTROL(para->cs1) | MCTL_CR_UNKNOWN |  in mctl_set_cr()
37 		MCTL_CR_CHANNEL(1) | MCTL_CR_DRAM_TYPE(para->dram_type) |  in mctl_set_cr()
38 		(para->seq ? MCTL_CR_SEQUENCE : 0) |  in mctl_set_cr()
39 		((para->bus_width == 16) ? MCTL_CR_BUSW16 : MCTL_CR_BUSW8) |  in mctl_set_cr()
40 		MCTL_CR_PAGE_SIZE(para->page_size) | MCTL_CR_ROW(para->rows) |  in mctl_set_cr()
41 		MCTL_CR_BANK(para->bank) | MCTL_CR_RANK(para->rank),  in mctl_set_cr()
45 static void auto_detect_dram_size(struct dram_para *para)  in auto_detect_dram_size()  argument
47 	u8 orig_rank = para->rank;  in auto_detect_dram_size()
51 	para->page_size = 512;  in auto_detect_dram_size()
52 	para->seq = 1;  in auto_detect_dram_size()
53 	para->rows = 16;  in auto_detect_dram_size()
54 	para->rank = 1;  in auto_detect_dram_size()
55 	mctl_set_cr(para);  in auto_detect_dram_size()
62 	para->rows = 11;  in auto_detect_dram_size()
63 	para->page_size = 8192;  in auto_detect_dram_size()
64 	mctl_set_cr(para);  in auto_detect_dram_size()
70 	para->seq = 0;  in auto_detect_dram_size()
71 	para->rank = orig_rank;  in auto_detect_dram_size()
72 	para->rows = rows;  in auto_detect_dram_size()
73 	para->page_size = 1 << columns;  in auto_detect_dram_size()
74 	mctl_set_cr(para);  in auto_detect_dram_size()
85 static void auto_set_timing_para(struct dram_para *para)  in auto_set_timing_para()  argument
131 	mctl_set_cr(para);  in auto_set_timing_para()
133 	if (para->dram_type == DRAM_TYPE_DDR3) {  in auto_set_timing_para()
138 	} else if (para->dram_type == DRAM_TYPE_LPDDR3) {  in auto_set_timing_para()
211 static void mctl_data_train_cfg(struct dram_para *para)  in mctl_data_train_cfg()  argument
216 	if (para->rank == 2)  in mctl_data_train_cfg()
222 static int mctl_train_dram(struct dram_para *para)  in mctl_train_dram()  argument
227 	mctl_data_train_cfg(para);  in mctl_train_dram()
257 static int mctl_channel_init(struct dram_para *para)  in mctl_channel_init()  argument
267 	auto_set_timing_para(para);  in mctl_channel_init()
314 	para->cs1 = 0;  in mctl_channel_init()
315 	para->rank = 2;  in mctl_channel_init()
316 	para->bus_width = 16;  in mctl_channel_init()
317 	mctl_set_cr(para);  in mctl_channel_init()
323 	if (para->dram_type == DRAM_TYPE_LPDDR3)  in mctl_channel_init()
331 	mctl_data_train_cfg(para);  in mctl_channel_init()
337 	if (para->dram_type == DRAM_TYPE_DDR3)  in mctl_channel_init()
343 	if (mctl_train_dram(para) != 0) {  in mctl_channel_init()
351 		para->rank = 1;  in mctl_channel_init()
352 		mctl_set_cr(para);  in mctl_channel_init()
359 			para->cs1 = 1;  in mctl_channel_init()
360 			mctl_set_cr(para);  in mctl_channel_init()
361 			if (mctl_train_dram(para) == 0)  in mctl_channel_init()
367 		para->cs1 = 0;  in mctl_channel_init()
368 		para->bus_width = 8;  in mctl_channel_init()
369 		mctl_set_cr(para);  in mctl_channel_init()
370 		if (mctl_train_dram(para) != 0)  in mctl_channel_init()
388 static void mctl_sys_init(struct dram_para *para)  in mctl_sys_init()  argument
415 	para->rank = 2;  in mctl_sys_init()
416 	para->bus_width = 16;  in mctl_sys_init()
417 	mctl_set_cr(para);  in mctl_sys_init()
432 	struct dram_para para = {  in sunxi_dram_init()  local
443 	para.dram_type = CONFIG_DRAM_TYPE;  in sunxi_dram_init()
453 	mctl_sys_init(&para);  in sunxi_dram_init()
455 	if (mctl_channel_init(&para) != 0)  in sunxi_dram_init()
458 	auto_detect_dram_size(&para);  in sunxi_dram_init()
464 	if (para.rank == 2)  in sunxi_dram_init()
469 	return para.page_size * (para.bus_width / 8) *  in sunxi_dram_init()
470 		(1 << (para.bank + para.rank + para.rows));  in sunxi_dram_init()