27 static void mctl_set_bit_delays(struct dram_para *para)  in mctl_set_bit_delays()  argument
37 			writel(DXBDLR_WRITE_DELAY(para->dx_write_delays[i][j]) |  in mctl_set_bit_delays()
38 			       DXBDLR_READ_DELAY(para->dx_read_delays[i][j]),  in mctl_set_bit_delays()
42 		writel(ACBDLR_WRITE_DELAY(para->ac_delays[i]),  in mctl_set_bit_delays()
267 static void mctl_h3_zq_calibration_quirk(struct dram_para *para)  in mctl_h3_zq_calibration_quirk()  argument
334 static void mctl_set_cr(uint16_t socid, struct dram_para *para)  in mctl_set_cr()  argument
349 	       (para->bank_bits == 3 ? MCTL_CR_EIGHT_BANKS : MCTL_CR_FOUR_BANKS) |  in mctl_set_cr()
350 	       MCTL_CR_BUS_FULL_WIDTH(para->bus_full_width) |  in mctl_set_cr()
351 	       (para->dual_rank ? MCTL_CR_DUAL_RANK : MCTL_CR_SINGLE_RANK) |  in mctl_set_cr()
352 	       MCTL_CR_PAGE_SIZE(para->page_size) |  in mctl_set_cr()
353 	       MCTL_CR_ROW_BITS(para->row_bits), &mctl_com->cr);  in mctl_set_cr()
356 		if (para->dual_rank)  in mctl_set_cr()
364 static void mctl_sys_init(uint16_t socid, struct dram_para *para)  in mctl_sys_init()  argument
419 static int mctl_channel_init(uint16_t socid, struct dram_para *para)  in mctl_channel_init()  argument
428 	mctl_set_cr(socid, para);  in mctl_channel_init()
429 	mctl_set_timing_params(socid, para);  in mctl_channel_init()
488 	if (!para->bus_full_width) {  in mctl_channel_init()
501 			(para->dual_rank ? 0x3 : 0x1) << 24);  in mctl_channel_init()
503 	mctl_set_bit_delays(para);  in mctl_channel_init()
507 		mctl_h3_zq_calibration_quirk(para);  in mctl_channel_init()
533 			para->dual_rank = 0;  in mctl_channel_init()
542 			para->bus_full_width = 0;  in mctl_channel_init()
547 			para->bus_full_width = 0;  in mctl_channel_init()
551 		mctl_set_cr(socid, para);  in mctl_channel_init()
584 static void mctl_auto_detect_dram_size(uint16_t socid, struct dram_para *para)  in mctl_auto_detect_dram_size()  argument
587 	para->page_size = 512;  in mctl_auto_detect_dram_size()
588 	para->row_bits = 16;  in mctl_auto_detect_dram_size()
589 	para->bank_bits = 2;  in mctl_auto_detect_dram_size()
590 	mctl_set_cr(socid, para);  in mctl_auto_detect_dram_size()
592 	for (para->row_bits = 11; para->row_bits < 16; para->row_bits++)  in mctl_auto_detect_dram_size()
593 		if (mctl_mem_matches((1 << (para->row_bits + para->bank_bits)) * para->page_size))  in mctl_auto_detect_dram_size()
597 	para->bank_bits = 3;  in mctl_auto_detect_dram_size()
598 	mctl_set_cr(socid, para);  in mctl_auto_detect_dram_size()
600 	for (para->bank_bits = 2; para->bank_bits < 3; para->bank_bits++)  in mctl_auto_detect_dram_size()
601 		if (mctl_mem_matches((1 << para->bank_bits) * para->page_size))  in mctl_auto_detect_dram_size()
605 	para->page_size = 8192;  in mctl_auto_detect_dram_size()
606 	mctl_set_cr(socid, para);  in mctl_auto_detect_dram_size()
608 	for (para->page_size = 512; para->page_size < 8192; para->page_size *= 2)  in mctl_auto_detect_dram_size()
609 		if (mctl_mem_matches(para->page_size))  in mctl_auto_detect_dram_size()
691 	struct dram_para para = {  in sunxi_dram_init()  local
726 	para.dual_rank = 0;  in sunxi_dram_init()
736 	mctl_sys_init(socid, &para);  in sunxi_dram_init()
737 	if (mctl_channel_init(socid, &para))  in sunxi_dram_init()
740 	if (para.dual_rank)  in sunxi_dram_init()
762 	mctl_auto_detect_dram_size(socid, &para);  in sunxi_dram_init()
763 	mctl_set_cr(socid, &para);  in sunxi_dram_init()
765 	return (1UL << (para.row_bits + para.bank_bits)) * para.page_size *  in sunxi_dram_init()
766 	       (para.dual_rank ? 2 : 1);  in sunxi_dram_init()