Lines Matching refs:divider
248 u64 divider = parent_rate * 2; in clk_get_divider() local
251 divider += rate - 1; in clk_get_divider()
252 do_div(divider, rate); in clk_get_divider()
254 if ((s64)divider - 2 < 0) in clk_get_divider()
257 if ((s64)divider - 2 >= max_divider) in clk_get_divider()
260 return divider - 2; in clk_get_divider()
300 int divider) in get_rate_from_divider() argument
305 do_div(rate, divider + 2); in get_rate_from_divider()
378 int divider = clk_get_divider(divider_bits, divided_parent, in find_best_divider() local
381 divider); in find_best_divider()
385 if (divider != -1 && error < best_error) { in find_best_divider()
388 best_divider = divider; in find_best_divider()
407 int mux_bits, unsigned divider) in adjust_periph_pll() argument
412 divider << OUT_CLK_DIVISOR_SHIFT); in adjust_periph_pll()
444 int divider; in clock_adjust_periph_pll_div() local
451 divider = find_best_divider(divider_bits, pll_rate[parent], in clock_adjust_periph_pll_div()
456 assert(divider >= 0); in clock_adjust_periph_pll_div()
457 if (adjust_periph_pll(periph_id, source, mux_bits, divider)) in clock_adjust_periph_pll_div()