25 static unsigned pll_rate[CLOCK_ID_COUNT];  variable
274 	div = clk_get_divider(8, pll_rate[clkid], rate);  in clock_set_pllout()
313 	unsigned parent_rate = pll_rate[parent];  in clock_get_periph_rate()
451 	divider = find_best_divider(divider_bits, pll_rate[parent],  in clock_adjust_periph_pll_div()
689 	pll_rate[CLOCK_ID_CGENERAL] = clock_get_rate(CLOCK_ID_CGENERAL);  in clock_init()
690 	pll_rate[CLOCK_ID_MEMORY] = clock_get_rate(CLOCK_ID_MEMORY);  in clock_init()
691 	pll_rate[CLOCK_ID_PERIPH] = clock_get_rate(CLOCK_ID_PERIPH);  in clock_init()
692 	pll_rate[CLOCK_ID_USB] = clock_get_rate(CLOCK_ID_USB);  in clock_init()
693 	pll_rate[CLOCK_ID_DISPLAY] = clock_get_rate(CLOCK_ID_DISPLAY);  in clock_init()
694 	pll_rate[CLOCK_ID_XCPU] = clock_get_rate(CLOCK_ID_XCPU);  in clock_init()
695 	pll_rate[CLOCK_ID_SFROM32KHZ] = 32768;  in clock_init()
696 	pll_rate[CLOCK_ID_OSC] = clock_get_rate(CLOCK_ID_OSC);  in clock_init()
697 	pll_rate[CLOCK_ID_CLK_M] = clock_get_rate(CLOCK_ID_CLK_M);  in clock_init()
699 	debug("Osc = %d\n", pll_rate[CLOCK_ID_OSC]);  in clock_init()
700 	debug("CLKM = %d\n", pll_rate[CLOCK_ID_CLK_M]);  in clock_init()
701 	debug("PLLC = %d\n", pll_rate[CLOCK_ID_CGENERAL]);  in clock_init()
702 	debug("PLLM = %d\n", pll_rate[CLOCK_ID_MEMORY]);  in clock_init()
703 	debug("PLLP = %d\n", pll_rate[CLOCK_ID_PERIPH]);  in clock_init()
704 	debug("PLLU = %d\n", pll_rate[CLOCK_ID_USB]);  in clock_init()
705 	debug("PLLD = %d\n", pll_rate[CLOCK_ID_DISPLAY]);  in clock_init()
706 	debug("PLLX = %d\n", pll_rate[CLOCK_ID_XCPU]);  in clock_init()