170 int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm,  in pllx_set_rate()  argument
179 	if (readl(&pll->pll_base) & PLL_ENABLE_MASK) {  in pllx_set_rate()
189 	writel(reg, &pll->pll_base);  in pllx_set_rate()
204 	writel(reg, &pll->pll_misc);  in pllx_set_rate()
207 	reg = readl(&pll->pll_base);  in pllx_set_rate()
209 	writel(reg, &pll->pll_base);  in pllx_set_rate()
213 	reg = readl(&pll->pll_misc);  in pllx_set_rate()
216 	writel(reg, &pll->pll_misc);  in pllx_set_rate()
220 	reg = readl(&pll->pll_base);  in pllx_set_rate()
222 	writel(reg, &pll->pll_base);  in pllx_set_rate()
231 	struct clk_pll_simple *pll = &clkrst->crc_pll_simple[SIMPLE_PLLX];  in init_pllx()  local
255 	pllx_set_rate(pll, sel->n, sel->m, sel->p, sel->cpcon);  in init_pllx()