410 static void umc_set_system_latency(void __iomem *dc_base, int phy_latency)  in umc_set_system_latency()  argument
415 	val = readl(dc_base + UMC_RDATACTL_D0);  in umc_set_system_latency()
433 	writel(val, dc_base + UMC_RDATACTL_D0);  in umc_set_system_latency()
434 	writel(val, dc_base + UMC_RDATACTL_D1);  in umc_set_system_latency()
436 	readl(dc_base + UMC_RDATACTL_D1); /* relax */  in umc_set_system_latency()
440 static void umc_refresh_ctrl(void __iomem *dc_base, int enable)  in umc_refresh_ctrl()  argument
444 	tmp = readl(dc_base + UMC_SPCSETB);  in umc_refresh_ctrl()
452 	writel(tmp, dc_base + UMC_SPCSETB);  in umc_refresh_ctrl()
464 static int umc_dc_init(void __iomem *dc_base, enum dram_freq freq,  in umc_dc_init()  argument
486 	writel(umc_cmdctla[freq], dc_base + UMC_CMDCTLA);  in umc_dc_init()
489 	       dc_base + UMC_CMDCTLB);  in umc_dc_init()
491 	writel(umc_spcctla[freq][size_e], dc_base + UMC_SPCCTLA);  in umc_dc_init()
492 	writel(umc_spcctlb[freq], dc_base + UMC_SPCCTLB);  in umc_dc_init()
507 	writel(val, dc_base + UMC_RDATACTL_D0);  in umc_dc_init()
509 		writel(val, dc_base + UMC_RDATACTL_D1);  in umc_dc_init()
511 	writel(0x04060A02, dc_base + UMC_WDATACTL_D0);  in umc_dc_init()
513 		writel(0x04060A02, dc_base + UMC_WDATACTL_D1);  in umc_dc_init()
514 	writel(0x04000000, dc_base + UMC_DATASET);  in umc_dc_init()
515 	writel(0x00400020, dc_base + UMC_DCCGCTL);  in umc_dc_init()
516 	writel(0x00000084, dc_base + UMC_FLOWCTLG);  in umc_dc_init()
517 	writel(0x00000000, dc_base + UMC_ACSSETA);  in umc_dc_init()
520 	       dc_base + UMC_FLOWCTLA);  in umc_dc_init()
522 	writel(0x00004400, dc_base + UMC_FLOWCTLC);  in umc_dc_init()
523 	writel(0x200A0A00, dc_base + UMC_SPCSETB);  in umc_dc_init()
524 	writel(0x00000520, dc_base + UMC_DFICUPDCTLA);  in umc_dc_init()
525 	writel(0x0000000D, dc_base + UMC_RESPCTL);  in umc_dc_init()
528 		writel(0x00202000, dc_base + UMC_FLOWCTLB);  in umc_dc_init()
529 		writel(0xFDBFFFFF, dc_base + UMC_FLOWCTLOB0);  in umc_dc_init()
530 		writel(0xFFFFFFFF, dc_base + UMC_FLOWCTLOB1);  in umc_dc_init()
531 		writel(0x00080700, dc_base + UMC_BSICMAPSET);  in umc_dc_init()
533 		writel(0x00200000, dc_base + UMC_FLOWCTLB);  in umc_dc_init()
534 		writel(0x00000000, dc_base + UMC_BSICMAPSET);  in umc_dc_init()
537 	writel(0x00000000, dc_base + UMC_ERRMASKA);  in umc_dc_init()
538 	writel(0x00000000, dc_base + UMC_ERRMASKB);  in umc_dc_init()
546 	void __iomem *dc_base = umc_ch_base + 0x00011000;  in umc_ch_init()  local
550 	writel(0x00000002, dc_base + UMC_INITSET);  in umc_ch_init()
551 	while (readl(dc_base + UMC_INITSTAT) & BIT(2))  in umc_ch_init()
556 	       dc_base + UMC_DIOCTLA);  in umc_ch_init()
568 	ret = umc_dc_init(dc_base, freq, size, width, ch);  in umc_ch_init()
581 	umc_set_system_latency(dc_base,  in umc_ch_init()
587 	umc_refresh_ctrl(dc_base, 0);  in umc_ch_init()
589 	umc_refresh_ctrl(dc_base, 1);  in umc_ch_init()