Lines Matching refs:move
16 move.w #0x2700,%sr; /* disable intrs */ \
108 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
111 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
115 move.l #0xFC008000, %a1
116 move.l #(CONFIG_SYS_CS0_BASE), (%a1)
117 move.l #0xFC008008, %a1
118 move.l #(CONFIG_SYS_CS0_CTRL), (%a1)
119 move.l #0xFC008004, %a1
120 move.l #(CONFIG_SYS_CS0_MASK), (%a1)
126 move.l #0xFC0A4074, %a1
127 move.b #(CONFIG_SYS_SDRAM_DRV_STRENGTH), (%a1)
131 move.l #0xFC0B8110, %a1
132 move.l #0xFC0B8114, %a2
135 move.l #0x13, %d1
136 move.l #(CONFIG_SYS_SDRAM_SIZE), %d2
148 move.l #(CONFIG_SYS_SDRAM_BASE), (%a1)
151 move.l #(CONFIG_SYS_SDRAM_BASE1), (%a2)
157 move.l #0xFC0B8008, %a1
158 move.l #(CONFIG_SYS_SDRAM_CFG1), (%a1)
160 move.l #0xFC0B800C, %a2
161 move.l #(CONFIG_SYS_SDRAM_CFG2), (%a2)
164 move.l #0xFC0B8000, %a1 /* Mode */
165 move.l #0xFC0B8004, %a2 /* Ctrl */
168 move.l #(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
172 move.l #(CONFIG_SYS_SDRAM_MODE), (%a1)
174 move.l #(CONFIG_SYS_SDRAM_EMOD), (%a1)
177 move.l #1000, %d0
184 move.l #(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
188 move.l #(CONFIG_SYS_SDRAM_CTRL + 4), %d0
190 move.l %d0, (%a2)
191 move.l %d0, (%a2)
194 move.l #(CONFIG_SYS_SDRAM_CTRL), %d0
197 move.l %d0, (%a2)
210 move.l #0xFC0A4036, %a0
211 move.b #0x3F, %d0
212 move.b %d0, (%a0)
216 move.b (%a0), %d0
218 move.b %d0, (%a0)
221 move.l #0xFC0A4037, %a0
222 move.b (%a0), %d0
224 move.b %d0, (%a0)
229 move.l #0xFC05C000, %a0
230 move.l #0x80FF0C00, (%a0) /* Master, clear TX/RX FIFO */
232 move.l #0xFC05C00C, %a0
233 move.l #0x3E000011, (%a0)
235 move.l #0xFC05C034, %a2 /* dtfr */
236 move.l #0xFC05C03B, %a3 /* drfr */
238 move.l #(ASM_SBF_IMG_HDR + 4), %a1
239 move.l (%a1)+, %d5
240 move.l (%a1), %a4
242 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_SBFHDR_DATA_OFFSET), %a0
243 move.l #(CONFIG_SYS_SBFHDR_SIZE), %d4
245 move.l #0xFC05C02C, %a1 /* dspi status */
248 move.l #0x8004000B, %d2 /* Fast Read Cmd */
252 move.l #0x80040000, %d2 /* Address byte 2 */
256 move.l #0x80040000, %d2 /* Address byte 1 */
260 move.l #0x80040000, %d2 /* Address byte 0 */
264 move.l #0x80040000, %d2 /* Dummy Wr and Rd */
270 move.l #0x80040000, %d2
274 move.b %d1, (%a0) /* read, copy to dst */
282 move.l #0x80040000, %d2
286 move.b %d1, (%a4) /* read, copy to dst */
292 move.l #0x00040000, %d2 /* Terminate */
297 move.l #(CONFIG_SYS_TEXT_BASE + 0x400), %a0
298 move.l %a0, (%a1)
302 move.l (%a1), %d0 /* status */
307 move.l %d2, (%a2)
311 move.l (%a1), %d0 /* status */
317 move.b (%a3), %d1
327 move.w #0x2700,%sr /* Mask off Interrupt */
331 move.l #CONFIG_SYS_TEXT_BASE, %d0
334 move.l #CONFIG_SYS_FLASH_BASE, %d0
337 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
342 move.l #CF_CACR_CINV, %d0 /* Invalidate cache cmd */
344 move.l #0, %d0
349 move.l #0, %d0
350 move.l #(ICACHE_STATUS), %a1 /* icache */
351 move.l #(DCACHE_STATUS), %a2 /* icache */
352 move.l %d0, (%a1)
353 move.l %d0, (%a2)
356 move.l #__got_start, %a5
359 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp
365 move.l %sp, -(%sp)
369 move.l %d0, %sp
370 move.l %sp, %fp
373 move.l %d0, -(%sp)
401 move.l 8(%a6), %sp /* set new stack pointer */
403 move.l 12(%a6), %d0 /* Save copy of Global Data pointer */
404 move.l 16(%a6), %a0 /* Save copy of Destination Address */
406 move.l #CONFIG_SYS_MONITOR_BASE, %a1
407 move.l #__init_end, %a2
408 move.l %a0, %a3
412 move.l (%a1)+, (%a3)+
420 move.l %a0, %a1
430 move.l %a0, %a1
432 move.l %a0, %d1
442 move.l %a0, %a1
444 move.l %a1,%a5 /* fix got pointer register a5 */
446 move.l %a0, %a2
450 move.l (%a1),%d1
453 move.l %d1,(%a1)+
458 move.l %a0, %a1
462 move.l %a0,-(%sp) /* dest_addr */
463 move.l %d0,-(%sp) /* gd */