Lines Matching refs:t1
102 lw t1, QCA953X_RESET_REG_RESET_MODULE(t0)
104 or t1, t1, t2
105 sw t1, QCA953X_RESET_REG_RESET_MODULE(t0)
107 lw t1, QCA953X_RESET_REG_RESET_MODULE(t0)
109 and t1, t1, t2
110 sw t1, QCA953X_RESET_REG_RESET_MODULE(t0)
115 li t1, 0x01
116 sw t1, QCA953X_RTC_REG_SYNC_RESET(t0)
122 lw t1, QCA953X_RTC_REG_SYNC_STATUS(t0)
123 andi t1, t1, 0x02
124 beqz t1, 1b
128 li t1, MK_DPLL2(2, 16)
129 sw t1, QCA953X_SRIF_BB_DPLL2_REG(t0)
130 sw t1, QCA953X_SRIF_PCIE_DPLL2_REG(t0)
131 sw t1, QCA953X_SRIF_DDR_DPLL2_REG(t0)
132 sw t1, QCA953X_SRIF_CPU_DPLL2_REG(t0)
135 lw t1, QCA953X_PLL_CLK_CTRL_REG(t0)
136 ori t1, PLL_CLK_CTRL_PLL_BYPASS
137 sw t1, QCA953X_PLL_CLK_CTRL_REG(t0)
140 li t1, PLL_CPU_CONF_VAL
141 sw t1, QCA953X_PLL_CPU_CONFIG_REG(t0)
144 li t1, PLL_DDR_CONF_VAL
145 sw t1, QCA953X_PLL_DDR_CONFIG_REG(t0)
148 li t1, PLL_CLK_CTRL_VAL
149 sw t1, QCA953X_PLL_CLK_CTRL_REG(t0)
152 lw t1, QCA953X_PLL_CPU_CONFIG_REG(t0)
154 and t1, t1, t2
155 sw t1, QCA953X_PLL_CPU_CONFIG_REG(t0)
158 lw t1, QCA953X_PLL_DDR_CONFIG_REG(t0)
160 and t1, t1, t2
161 sw t1, QCA953X_PLL_DDR_CONFIG_REG(t0)
164 lw t1, QCA953X_PLL_CLK_CTRL_REG(t0)
166 and t1, t1, t2
167 sw t1, QCA953X_PLL_CLK_CTRL_REG(t0)
170 li t1, PLL_DDR_DIT_FRAC_VAL
171 sw t1, QCA953X_PLL_DDR_DIT_FRAC_REG(t0)
174 li t1, PLL_CPU_DIT_FRAC_VAL
175 sw t1, QCA953X_PLL_CPU_DIT_FRAC_REG(t0)
179 lui t1, 0x03fc
180 sw t1, 0xb4(t0)