Lines Matching refs:r3
32 mfspr r3, SPRN_HDBCR0
33 oris r3, r3, 0x0080
34 mtspr SPRN_HDBCR0, r3
37 lis r3, HID0_EMCP@h /* enable machine check */
39 ori r3,r3,HID0_TBEN@l /* enable Timebase */
42 ori r3,r3,HID0_ENMAS7@l /* enable MAS7 updates */
44 mtspr SPRN_HID0,r3
47 li r3,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */
53 ori r3, r3, HID1_MBDD@l
55 mtspr SPRN_HID1,r3
59 mfspr r3,SPRN_HDBCR1
60 oris r3,r3,0x0100
61 mtspr SPRN_HDBCR1,r3
65 mfspr r3,SPRN_SVR
66 rlwinm r3,r3,0,0xff
68 cmpw r3,r4
73 cmpw r3,r4
83 mfspr r3,SPRN_HDBCR0
85 rlwimi r3,r4,0,0x1f8
86 mtspr SPRN_HDBCR0,r3
92 lis r3,BUCSR_ENABLE@h
93 ori r3,r3,BUCSR_ENABLE@l
94 mtspr SPRN_BUCSR,r3
97 li r3,0
98 mttbl r3
99 mttbu r3
106 mfspr r3,SPRN_L1CSR1
107 and. r1,r3,r2
110 lis r3,(L1CSR1_CPE|L1CSR1_ICE)@h
111 ori r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l
112 mtspr SPRN_L1CSR1,r3
115 mfspr r3,SPRN_L1CSR1
116 andi. r1,r3,L1CSR1_ICE@l
124 mfspr r3,SPRN_L1CSR0
125 and. r1,r3,r2
128 lis r3,(L1CSR0_CPE|L1CSR0_DCE)@h
129 ori r3,r3,(L1CSR0_CPE|L1CSR0_DCE)@l
130 mtspr SPRN_L1CSR0,r3
133 mfspr r3,SPRN_L1CSR0
134 andi. r1,r3,L1CSR0_DCE@l
140 lis r3,toreset(__spin_table_addr)@h
141 ori r3,r3,toreset(__spin_table_addr)@l
142 lwz r3,0(r3)
189 add r10,r3,r8
213 mfspr r3,SPRN_SVR
214 rlwinm r6,r3,24,~0x800 /* clear E bit */
221 rlwinm r3,r3,0,0xf0
223 cmpw r3,r5
227 lis r3,toreset(enable_cpu_a011_workaround)@ha
228 lwz r3,toreset(enable_cpu_a011_workaround)@l(r3)
229 cmpwi r3,0
232 mfspr r3,L1CSR2
233 oris r3,r3,(L1CSR2_DCWS)@h
234 mtspr L1CSR2,r3
244 mfspr r3,L1CSR2
245 andis. r3,r3,(L1CSR2_DCWS)@h
247 mfspr r3, SPRN_HDBCR0
248 oris r3, r3, 0x8000
249 mtspr SPRN_HDBCR0, r3
255 mfspr r3,SPRN_SVR
256 rlwinm r6,r3,24,~0x800 /* clear E bit of SVR */
258 lis r3,SVR_P2040@h
259 ori r3,r3,SVR_P2040@l
260 cmpw r6,r3
269 mfspr r3,SPRN_L2CSR0
270 and. r1,r3,r2
275 addi r3,r8,1
276 mtspr SPRN_L2CSR1,r3
279 lis r3,CONFIG_SYS_INIT_L2CSR0@h
280 ori r3,r3,CONFIG_SYS_INIT_L2CSR0@l
281 mtspr SPRN_L2CSR0,r3
284 mfspr r3,SPRN_L2CSR0
285 andis. r1,r3,L2CSR0_L2E@h
360 lis r3,(spin_table_compat - __second_half_boot_page)@h
361 ori r3,r3,(spin_table_compat - __second_half_boot_page)@l
362 add r3,r3,r11 /* r11 has the address of __second_half_boot_page */
363 lwz r14,0(r3)
385 li r3,0
388 stw r3,ENTRY_ADDR_UPPER(r10)
389 stw r3,ENTRY_R3_UPPER(r10)
391 stw r3,ENTRY_RESV(r10)
439 ld r3,ENTRY_R3_UPPER(r10)
441 lwz r3,ENTRY_R3_LOWER(r10)