Lines Matching refs:r3
87 mr r24, r3
90 mfspr r3,SPRN_SVR
91 rlwinm r3,r3,0,0xff
93 cmpw r3,r4
98 cmpw r3,r4
110 mfspr r3,SPRN_HDBCR0
112 rlwimi r3,r4,0,0x1f8
113 mtspr SPRN_HDBCR0,r3
120 mfspr r3, SPRN_HDBCR0
121 oris r3, r3, 0x0080
122 mtspr SPRN_HDBCR0, r3
134 mfspr r3, SPRN_L2CSR0
137 and. r4, r3, r2
140 mfspr r3, SPRN_L2CSR0
144 or r3, r2, r3
147 mtspr SPRN_L2CSR0,r3
150 mfspr r3, SPRN_L2CSR0
151 and. r1, r3, r2
154 mfspr r3, SPRN_L2CSR0
157 andc r4, r3, r2
315 mfspr r3,PVR
316 andi. r3,r3, 0xff
317 cmpwi r3,0x50@l /* if we are rev 5.0 or greater set MBDD */
326 mfspr r3,SPRN_HDBCR1
327 oris r3,r3,0x0100
328 mtspr SPRN_HDBCR1,r3
402 mfspr r3, MAS1
404 andc r3, r3, r2 /* Clear the TSIZE bits */
405 ori r3, r3, MAS1_TSIZE(BOOKE_PAGESZ_4K)@l
406 oris r3, r3, MAS1_IPROT@h
407 mtspr MAS1, r3
413 lis r3, MAS2_EPN@h
414 ori r3, r3, MAS2_EPN@l /* R3 = MAS2_EPN */
416 and r1, r1, r3 /* Our PC, rounded down to the nearest page */
419 andc r2, r2, r3
432 andc r2, r2, r3
451 li r3, 0
452 mtspr MAS1, r3
453 1: cmpw r3, r14
454 rlwinm r5, r3, 16, MAS0_ESEL_MSK
455 addi r3, r3, 1
466 2: cmpw r3, r4
535 CONFIG_SYS_CCSRBAR_PHYS_HIGH, r3
545 0, r3 /* The default CCSR address is always a 32-bit number */
695 delete_tlb0_entry 0, CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G, r3
696 delete_tlb0_entry 1, CONFIG_SYS_CCSRBAR + 0x1000, MAS2_I|MAS2_G, r3
710 CONFIG_SYS_CCSRBAR_PHYS_HIGH, r3
714 lis r3, (CONFIG_SYS_CCSRBAR + 0xC20000)@h
715 ori r3, r3, (CONFIG_SYS_CCSRBAR + 0xC20000)@l
717 stw r4, 4(r3)
721 stw r4, 0(r3) /* invalidate L2 */
724 lwz r0, 0(r3)
734 stw r4, 0(r3) /* enable L2 parity/ECC error checking */
737 lwz r0, 0(r3)
746 stw r4, 0(r3) /* enable L2 */
749 lwz r0, 0(r3)
756 delete_tlb0_entry 0, CONFIG_SYS_CCSRBAR + 0xC20000, MAS2_I|MAS2_G, r3
775 mfspr r3,SPRN_L1CSR1
776 and. r1,r3,r2
779 lis r3,(L1CSR1_CPE|L1CSR1_ICE)@h
780 ori r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l
781 mtspr SPRN_L1CSR1,r3
784 mfspr r3,SPRN_L1CSR1
785 andi. r1,r3,L1CSR1_ICE@l
793 mfspr r3,SPRN_L1CSR0
794 and. r1,r3,r2
797 lis r3,(L1CSR0_CPE|L1CSR0_DCE)@h
798 ori r3,r3,(L1CSR0_CPE|L1CSR0_DCE)@l
799 mtspr SPRN_L1CSR0,r3
802 mfspr r3,SPRN_L1CSR0
803 andi. r1,r3,L1CSR0_DCE@l
830 lis r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@h
831 ori r3, r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@l
837 mtspr MAS3, r3
846 lis r3, DCSRBAR_LAWAR@h
847 ori r3, r3, DCSRBAR_LAWAR@l
852 stw r3, 0xc08(r7) /* LAWAR0 */
855 lwz r3, 0xc08(r7) /* LAWAR0 */
867 li r3, MAS3_SW|MAS3_SR
872 mtspr MAS3, r3
881 li r3, 1
883 stw r3, CTBENR@l(r4)
884 lwz r3, CTBENR@l(r4)
885 twi 0,r3,0
889 addis r3, r7, \offset@ha
891 addi r3, r3, \offset@l
897 addis r3, r6, \offset@ha
899 addi r3, r3, \offset@l
919 2: mflr r3
920 tlbsx 0, r3
931 lis r3,(L1CSR1_ICFI|L1CSR1_ICLFR)@h
932 ori r3,r3,(L1CSR1_ICFI|L1CSR1_ICLFR)@l
935 mtspr SPRN_L1CSR1,r3
939 and. r4,r4,r3
942 lis r3,(L1CSR1_CPE|L1CSR1_ICE)@h
943 ori r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l
946 mtspr SPRN_L1CSR1,r3
950 and. r4,r4,r3
956 li r3, 0
958 mtspr MAS1, r3
964 li r3, 0
965 stw r3, 0xc08(r7) /* LAWAR0 */
966 lwz r3, 0xc08(r7)
971 li r3, 0
973 mtspr MAS1, r3
1023 stw r4, 0(r3)
1137 lis r3,CONFIG_SYS_INIT_RAM_ADDR@h
1138 ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
1146 dcbz r0,r3
1148 dcbtls 2, r0, r3
1149 dcbtls 0, r0, r3
1151 dcbtls 0, r0, r3
1153 addi r3,r3,CONFIG_SYS_CACHELINE_SIZE
1163 lis r3,CONFIG_SYS_MONITOR_BASE@h
1164 ori r3,r3,CONFIG_SYS_MONITOR_BASE@l
1165 addi r3,r3,_start_cont - _start
1166 mtlr r3
1182 lis r3,(CONFIG_SYS_INIT_RAM_ADDR)@h
1183 ori r3,r3,((CONFIG_SYS_INIT_SP_OFFSET-16)&~0xf)@l /* Align to 16 */
1191 subi r3,r3,((CONFIG_VAL(SYS_MALLOC_F_LEN)+16+15)&~0xf)
1202 cmplw r4,r3
1209 addi r3,r3,16 /* Pre-relocation malloc area */
1210 stw r3,GD_MALLOC_BASE(r4)
1211 subi r3,r3,16
1214 stw r0,0(r3) /* Terminate Back Chain */
1215 stw r0,+4(r3) /* NULL return address. */
1216 mr r1,r3 /* Transfer to SP(r1) */
1221 mr r3, r24
1226 lis r3,(MSR_CE|MSR_ME|MSR_DE)@h
1227 ori r3,r3,(MSR_CE|MSR_ME|MSR_DE)@l
1228 mtmsr r3
1263 addi r3,r1,STACK_FRAME_OVERHEAD
1270 addi r3,r1,STACK_FRAME_OVERHEAD
1384 lis r3,0
1385 ori r3,r3,L1CSR1_ICE
1386 andc r0,r0,r3
1393 mfspr r3,L1CSR1
1394 andi. r3,r3,L1CSR1_ICE
1414 mfspr r3,L1CSR0
1417 andc r3,r3,r4
1418 mtspr L1CSR0,r3
1424 mfspr r3,L1CSR0
1425 andi. r3,r3,L1CSR0_DCE
1434 lbz r3,0x0000(r3)
1443 stb r4,0x0000(r3)
1453 sth r4,0x0000(r3)
1463 sthbrx r4,r0,r3
1473 stw r4,0x0000(r3)
1483 stwbrx r4,r0,r3
1493 lhz r3,0x0000(r3)
1502 lhbrx r3,r0,r3
1520 lwbrx r3,r0,r3
1531 mtspr MAS0,r3
1538 li r3,0
1540 mtspr MAS8,r3
1561 mr r1,r3 /* Set new stack pointer */
1567 mr r3,r5 /* Destination Address */
1592 cmplw cr1,r3,r4
1601 la r7,-4(r3)
1609 add r7,r3,r0
1619 add r5,r3,r5
1622 andc r3,r3,r0
1623 mr r4,r3
1629 mr r4,r3
1668 la r3,GOT(_GOT2_TABLE_)
1671 sub r11,r3,r11
1672 addi r3,r3,-4
1673 1: lwzu r0,4(r3)
1677 stw r0,0(r3)
1685 lwz r3,GOT(_FIXUP_TABLE_)
1688 addi r3,r3,-4
1690 3: lwzu r4,4(r3)
1694 stw r4,0(r3)
1703 lwz r3,GOT(__bss_start)
1706 cmplw 0,r3,r4
1711 stw r0,0(r3)
1712 addi r3,r3,4
1713 cmplw 0,r3,r4
1717 mr r3,r9 /* Init Data pointer */
1735 mtspr IVPR,r3
1775 lis r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@h
1776 ori r3,r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@l
1781 1: dcbi r0,r3
1783 dcblc 2, r0, r3
1784 dcblc 0, r0, r3
1786 dcblc r0,r3
1788 addi r3,r3,CONFIG_SYS_CACHELINE_SIZE
1793 lis r3,CONFIG_SYS_INIT_RAM_ADDR@h
1794 ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
1795 tlbivax 0,r3
1796 addi r3,r3,0x1000
1797 tlbivax 0,r3
1798 addi r3,r3,0x1000
1799 tlbivax 0,r3
1800 addi r3,r3,0x1000
1801 tlbivax 0,r3
1807 mfspr r3,SPRN_L1CFG0
1809 rlwinm r5,r3,9,3 /* Extract cache block size */
1819 rlwinm r7,r3,0,0xff /* Extract number of KiB in the cache */
1834 1: lwz r3,0(r4) /* Load... */