Lines Matching refs:r3
36 mfspr r3,HID0
37 ori r3,r3,HID0_ICFI
38 mtspr HID0,r3
46 mfspr r3,HID0
47 ori r3,r3,HID0_DCFI
48 mtspr HID0,r3
56 lis r3,0
59 cmp 0,1,r3,r5
61 lwz r5,0(r3)
63 addi r3,r3,0x4
76 andc r3,r3,r5
77 subf r4,r3,r4
82 mr r6,r3
83 1: dcbst 0,r3
84 addi r3,r3,CACHE_LINE_SIZE
103 andc r3,r3,r5 /* align r3 down to cache line */
104 subf r4,r3,r4 /* r4 = offset of stop from start of cache line */
111 1: dcbst 0,r3
112 addi r3,r3,CACHE_LINE_SIZE
125 rlwinm r3,r3,0,0,19 /* Get page base address */
128 mr r6,r3
129 0: dcbst 0,r3 /* Write line to ram */
130 addi r3,r3,CACHE_LINE_SIZE
151 1: icbi 0,r3
152 addi r3,r3,CACHE_LINE_SIZE
166 1: dcbz 0,r3
167 addi r3,r3,CACHE_LINE_SIZE
175 mfspr r3, HID0
177 andc r3, r3, r5
178 ori r3, r3, HID0_ICE
179 ori r5, r3, HID0_ICFI
181 mtspr HID0, r3
193 mfspr r3, HID0
196 andc r3, r3, r5
197 mtspr HID0, r3
205 mfspr r3, HID0
206 andi. r3, r3, HID0_ICE
211 mfspr r3, HID0
213 andc r3, r3, r5
214 mtspr HID0, r3 /* no invalidate, unlock */
215 ori r3, r3, HID0_DCE
216 ori r5, r3, HID0_DCFI
218 mtspr HID0, r3 /* enable */
227 mfspr r3, HID0
229 andc r3, r3, r5
230 mtspr HID0, r3 /* no invalidate, unlock */
231 ori r3, r3, HID0_DCE
232 ori r5, r3, HID0_DCFI
234 mtspr HID0, r3 /* enable */
254 mfspr r3, HID0
256 andc r3, r3, r5
257 mtspr HID0, r3 /* no invalidate, unlock */
259 andc r3, r3, r5 /* no enable, no invalidate */
260 mtspr HID0, r3
272 mfspr r3, HID0
273 andi. r3, r3, HID0_DCE
280 mfspr r3, l2cr
281 rlwinm. r3, r3, 0, 0, 0
284 mfspr r3, l2cr
285 rlwinm r3, r3, 0, 1, 31
291 mtspr l2cr, r3
293 1: mfspr r3, l2cr
294 oris r3, r3, L2CR_L2I@h
295 mtspr l2cr, r3
298 mfspr r3, l2cr
299 andis. r3, r3, L2CR_L2I@h
311 lis r3, L2_ENABLE@h
312 ori r3, r3, L2_ENABLE@l
313 mtspr l2cr, r3
328 lis r3, L2_INIT@h
329 ori r3, r3, L2_INIT@l
330 mtspr l2cr, r3