Lines Matching refs:ch
255 uint8_t ch; /* channel counter */ in ddrphy_init() local
279 for (ch = 0; ch < NUM_CHANNELS; ch++) { in ddrphy_init()
280 if (mrc_params->channel_enables & (1 << ch)) { in ddrphy_init()
283 CMDPMCONFIG0 + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
287 CMDCFGREG0 + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
291 CMDPTRREG + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
303 for (ch = 0; ch < NUM_CHANNELS; ch++) { in ddrphy_init()
304 if (mrc_params->channel_enables & (1 << ch)) { in ddrphy_init()
313 ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
336 ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
342 ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
367 ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
389 ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
395 ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
413 ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
419 ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
428 ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
434 ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
442 ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
447 ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
454 ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
459 ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
467 ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
474 ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
481 ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
487 ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
493 CMDOBSCKEBBCTL + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
498 CMDCFGREG0 + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
503 CMDRCOMPODT + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
510 CMDPMDLYREG4 + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
518 CMDPMDLYREG3 + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
522 CMDPMDLYREG2 + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
526 CMDPMDLYREG1 + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
530 CMDPMDLYREG0 + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
534 CMDPMCONFIG0 + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
539 CMDMDLLCTL + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
544 CCOBSCKEBBCTL + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
548 CCCFGREG0 + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
552 CCRCOMPODT + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
556 CCMDLLCTL + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
567 DQVREFCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
571 CMDVREFCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
575 CLKVREFCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
579 DQSVREFCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
583 CTLVREFCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
588 COMPEN1CH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
594 DQVREFCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
598 DQSVREFCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
602 CLKVREFCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
615 DLYSELCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
619 TCOVREFCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
624 CCBUFODTCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
629 COMPEN0CH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
636 DQDRVPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
641 DQDRVPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
646 DQDLYPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
651 DQDLYPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
656 DQODTPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
661 DQODTPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
666 DQTCOPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
670 DQTCOPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
676 DQSDRVPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
681 DQSDRVPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
686 DQSDLYPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
691 DQSDLYPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
696 DQSODTPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
701 DQSODTPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
706 DQSTCOPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
710 DQSTCOPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
716 CLKDRVPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
721 CLKDRVPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
726 CLKDLYPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
731 CLKDLYPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
736 CLKODTPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
741 CLKODTPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
746 CLKTCOPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
750 CLKTCOPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
756 CMDDRVPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
761 CMDDRVPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
766 CMDDLYPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
771 CMDDLYPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
778 CTLDRVPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
783 CTLDRVPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
788 CTLDLYPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
793 CTLDLYPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
800 DQTCOPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
805 DQTCOPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
812 DQSTCOPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
817 DQSTCOPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
824 CLKTCOPUCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
829 CLKTCOPDCTLCH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
836 set_wcmd(ch, ddr_wcmd[PLATFORM_ID]); in ddrphy_init()
838 set_wcmd(ch, ddr_wclk[PLATFORM_ID] + HALF_CLK); in ddrphy_init()
843 set_wclk(ch, rk, ddr_wclk[PLATFORM_ID]); in ddrphy_init()
845 set_wctl(ch, rk, ddr_wctl[PLATFORM_ID]); in ddrphy_init()
847 set_wctl(ch, rk, ddr_wclk[PLATFORM_ID] + HALF_CLK); in ddrphy_init()
934 for (ch = 0; ch < NUM_CHANNELS; ch++) { in ddrphy_init()
935 if (mrc_params->channel_enables & (1 << ch)) { in ddrphy_init()
943 ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
955 CMDMDLLCTL + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
960 CCMDLLCTL + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
970 for (ch = 0; ch < NUM_CHANNELS; ch++) { in ddrphy_init()
971 if (mrc_params->channel_enables & (1 << ch)) { in ddrphy_init()
979 ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
991 CMDMDLLCTL + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
996 CCMDLLCTL + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
1006 for (ch = 0; ch < NUM_CHANNELS; ch++) { in ddrphy_init()
1007 if (mrc_params->channel_enables & (1 << ch)) { in ddrphy_init()
1023 ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
1030 ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
1037 ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
1049 CMDDLLTXCTL + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
1058 for (ch = 0; ch < NUM_CHANNELS; ch++) { in ddrphy_init()
1059 if (mrc_params->channel_enables & (1 << ch)) { in ddrphy_init()
1068 ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
1074 ECCCLKALIGNREG2 + ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
1077 CMDCLKALIGNREG2 + ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
1080 CCCLKALIGNREG2 + ch * DDRIODQ_CH_OFFSET, in ddrphy_init()
1083 CMDCLKALIGNREG0 + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
1090 CMDCLKALIGNREG1 + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
1096 CMDCLKALIGNREG2 + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
1102 CMDCLKALIGNREG0 + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
1105 CMDCLKALIGNREG0 + ch * DDRIOCCC_CH_OFFSET) & in ddrphy_init()
1112 CMDPTRREG + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
1118 COMPEN0CH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
1127 COMPEN0CH0 + ch * DDRCOMP_CH_OFFSET, in ddrphy_init()
1134 CMDCFGREG0 + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
1139 CMDPMCONFIG0 + ch * DDRIOCCC_CH_OFFSET, in ddrphy_init()
1353 uint8_t ch, rk, bl; in restore_timings() local
1356 for (ch = 0; ch < NUM_CHANNELS; ch++) { in restore_timings()
1359 set_rcvn(ch, rk, bl, mt->rcvn[ch][rk][bl]); in restore_timings()
1360 set_rdqs(ch, rk, bl, mt->rdqs[ch][rk][bl]); in restore_timings()
1361 set_wdqs(ch, rk, bl, mt->wdqs[ch][rk][bl]); in restore_timings()
1362 set_wdq(ch, rk, bl, mt->wdq[ch][rk][bl]); in restore_timings()
1365 set_vref(ch, bl, mt->vref[ch][bl]); in restore_timings()
1368 set_wctl(ch, rk, mt->wctl[ch][rk]); in restore_timings()
1370 set_wcmd(ch, mt->wcmd[ch]); in restore_timings()
1382 uint8_t ch, rk, bl; in default_timings() local
1384 for (ch = 0; ch < NUM_CHANNELS; ch++) { in default_timings()
1387 set_rdqs(ch, rk, bl, 24); in default_timings()
1390 set_vref(ch, bl, 32); in default_timings()
1404 uint8_t ch; /* channel counter */ in rcvn_cal() local
1445 for (ch = 0; ch < NUM_CHANNELS; ch++) { in rcvn_cal()
1446 if (mrc_params->channel_enables & (1 << ch)) { in rcvn_cal()
1454 mrc_post_code(0x05, 0x10 + ((ch << 4) | rk)); in rcvn_cal()
1459 set_rcvn(ch, rk, bl, ddr_rcvn[PLATFORM_ID]); in rcvn_cal()
1466 ch * DDRIODQ_CH_OFFSET, in rcvn_cal()
1474 set_rcvn(ch, rk, bl, delay[bl]); in rcvn_cal()
1478 find_rising_edge(mrc_params, delay, ch, rk, true); in rcvn_cal()
1483 set_rcvn(ch, rk, bl, delay[bl]); in rcvn_cal()
1487 temp = sample_dqs(mrc_params, ch, rk, true); in rcvn_cal()
1492 set_rcvn(ch, rk, bl, delay[bl]); in rcvn_cal()
1495 training_message(ch, rk, bl); in rcvn_cal()
1509 final_delay[ch][bl] += delay[bl]; in rcvn_cal()
1511 set_rcvn(ch, rk, bl, final_delay[ch][bl] / num_ranks_enabled); in rcvn_cal()
1517 set_rcvn(ch, rk, bl, delay[bl]); in rcvn_cal()
1526 ch * DDRIODQ_CH_OFFSET, in rcvn_cal()
1551 uint8_t ch; /* channel counter */ in wr_level() local
1591 for (ch = 0; ch < NUM_CHANNELS; ch++) { in wr_level()
1592 if (mrc_params->channel_enables & (1 << ch)) { in wr_level()
1600 mrc_post_code(0x06, 0x10 + ((ch << 4) | rk)); in wr_level()
1604 set_wdqs(ch, rk, bl, ddr_wdqs[PLATFORM_ID]); in wr_level()
1605 set_wdq(ch, rk, bl, ddr_wdqs[PLATFORM_ID] - QRTR_CLK); in wr_level()
1636 DQCTL + DDRIODQ_BL_OFFSET * bl + DDRIODQ_CH_OFFSET * ch, in wr_level()
1643 CCDDR3RESETCTL + DDRIOCCC_CH_OFFSET * ch, in wr_level()
1652 delay[bl] = get_wclk(ch, rk); in wr_level()
1654 set_wdqs(ch, rk, bl, delay[bl]); in wr_level()
1658 find_rising_edge(mrc_params, delay, ch, rk, false); in wr_level()
1662 CCDDR3RESETCTL + DDRIOCCC_CH_OFFSET * ch, in wr_level()
1668 DQCTL + DDRIODQ_BL_OFFSET * bl + DDRIODQ_CH_OFFSET * ch, in wr_level()
1688 mrc_post_code(0x06, 0x30 + ((ch << 4) | rk)); in wr_level()
1700 delay[bl] = get_wdqs(ch, rk, bl) + FULL_CLK; in wr_level()
1701 set_wdqs(ch, rk, bl, delay[bl]); in wr_level()
1706 set_wdq(ch, rk, bl, (delay[bl] - QRTR_CLK)); in wr_level()
1710 address = get_addr(ch, rk); in wr_level()
1725 set_wdqs(ch, rk, bl, delay[bl]); in wr_level()
1727 set_wdq(ch, rk, bl, delay[bl] - QRTR_CLK); in wr_level()
1737 final_delay[ch][bl] += delay[bl]; in wr_level()
1738 set_wdqs(ch, rk, bl, final_delay[ch][bl] / num_ranks_enabled); in wr_level()
1740 set_wdq(ch, rk, bl, final_delay[ch][bl] / num_ranks_enabled - QRTR_CLK); in wr_level()
1786 uint8_t ch; /* channel counter */ in rd_train() local
1819 for (ch = 0; ch < NUM_CHANNELS; ch++) { in rd_train()
1820 if (mrc_params->channel_enables & (1 << ch)) { in rd_train()
1826 set_rdqs(ch, rk, bl, ddr_rdqs[PLATFORM_ID]); in rd_train()
1834 for (ch = 0; ch < NUM_CHANNELS; ch++) { in rd_train()
1835 if (mrc_params->channel_enables & (1 << ch)) { in rd_train()
1842 x_coordinate[L][B][ch][rk][bl] = RDQS_MIN; in rd_train()
1843 x_coordinate[R][B][ch][rk][bl] = RDQS_MAX; in rd_train()
1844 x_coordinate[L][T][ch][rk][bl] = RDQS_MIN; in rd_train()
1845 x_coordinate[R][T][ch][rk][bl] = RDQS_MAX; in rd_train()
1847 y_coordinate[L][B][ch][bl] = VREF_MIN; in rd_train()
1848 y_coordinate[R][B][ch][bl] = VREF_MIN; in rd_train()
1849 y_coordinate[L][T][ch][bl] = VREF_MAX; in rd_train()
1850 y_coordinate[R][T][ch][bl] = VREF_MAX; in rd_train()
1872 for (ch = 0; ch < NUM_CHANNELS; ch++) { in rd_train()
1873 if (mrc_params->channel_enables & (0x1 << ch)) { in rd_train()
1881 set_rdqs(ch, rk, bl, in rd_train()
1882 x_coordinate[side_x][side_y][ch][rk][bl]); in rd_train()
1883 set_vref(ch, bl, in rd_train()
1884 y_coordinate[side_x][side_y][ch][bl]); in rd_train()
1888 address = get_addr(ch, rk); in rd_train()
1906 x_coordinate[L][side_y][ch][rk][bl] += RDQS_STEP; in rd_train()
1908 x_coordinate[R][side_y][ch][rk][bl] -= RDQS_STEP; in rd_train()
1911 if ((x_coordinate[L][side_y][ch][rk][bl] > (RDQS_MAX - MIN_RDQS_EYE)) || in rd_train()
1912 (x_coordinate[R][side_y][ch][rk][bl] < (RDQS_MIN + MIN_RDQS_EYE)) || in rd_train()
1913 (x_coordinate[L][side_y][ch][rk][bl] == in rd_train()
1914 x_coordinate[R][side_y][ch][rk][bl])) { in rd_train()
1920 y_coordinate[side_x][B][ch][bl] += VREF_STEP; in rd_train()
1922 y_coordinate[side_x][T][ch][bl] -= VREF_STEP; in rd_train()
1925 if ((y_coordinate[side_x][B][ch][bl] > (VREF_MAX - MIN_VREF_EYE)) || in rd_train()
1926 (y_coordinate[side_x][T][ch][bl] < (VREF_MIN + MIN_VREF_EYE)) || in rd_train()
1927 (y_coordinate[side_x][B][ch][bl] == y_coordinate[side_x][T][ch][bl])) { in rd_train()
1929 training_message(ch, rk, bl); in rd_train()
1933 set_vref(ch, bl, y_coordinate[side_x][side_y][ch][bl]); in rd_train()
1935 x_coordinate[side_x][side_y][ch][rk][bl] = in rd_train()
1941 set_rdqs(ch, rk, bl, x_coordinate[side_x][side_y][ch][rk][bl]); in rd_train()
1956 for (ch = 0; ch < NUM_CHANNELS; ch++) { in rd_train()
1957 if (mrc_params->channel_enables & (1 << ch)) { in rd_train()
1968 x_coordinate[L][T][ch][rk][bl], in rd_train()
1969 x_coordinate[R][T][ch][rk][bl], in rd_train()
1970 x_coordinate[L][B][ch][rk][bl], in rd_train()
1971 x_coordinate[R][B][ch][rk][bl]); in rd_train()
1974 temp1 = (x_coordinate[R][T][ch][rk][bl] + x_coordinate[L][T][ch][rk][bl]) / 2; in rd_train()
1976 temp2 = (x_coordinate[R][B][ch][rk][bl] + x_coordinate[L][B][ch][rk][bl]) / 2; in rd_train()
1978 x_center[ch][rk][bl] = (uint8_t) ((temp1 + temp2) / 2); in rd_train()
1984 y_coordinate[R][B][ch][bl], in rd_train()
1985 y_coordinate[R][T][ch][bl], in rd_train()
1986 y_coordinate[L][B][ch][bl], in rd_train()
1987 y_coordinate[L][T][ch][bl]); in rd_train()
1990 temp1 = (y_coordinate[R][T][ch][bl] + y_coordinate[R][B][ch][bl]) / 2; in rd_train()
1992 temp2 = (y_coordinate[L][T][ch][bl] + y_coordinate[L][B][ch][bl]) / 2; in rd_train()
1994 y_center[ch][bl] = (uint8_t) ((temp1 + temp2) / 2); in rd_train()
2008 for (ch = 0; ch < NUM_CHANNELS; ch++) { in rd_train()
2009 if (mrc_params->channel_enables & (1 << ch)) { in rd_train()
2014 set_rdqs(ch, rk, bl, x_center[ch][rk][bl] - (MIN_RDQS_EYE / 2)); in rd_train()
2016 set_rdqs(ch, rk, bl, x_center[ch][rk][bl] + (MIN_RDQS_EYE / 2)); in rd_train()
2019 set_vref(ch, bl, y_center[ch][bl] - (MIN_VREF_EYE / 2)); in rd_train()
2021 set_vref(ch, bl, y_center[ch][bl] + (MIN_VREF_EYE / 2)); in rd_train()
2043 for (ch = 0; ch < NUM_CHANNELS; ch++) { in rd_train()
2044 if (mrc_params->channel_enables & (1 << ch)) { in rd_train()
2054 final_delay[ch][bl] += x_center[ch][rk][bl]; in rd_train()
2055 set_rdqs(ch, rk, bl, final_delay[ch][bl] / num_ranks_enabled); in rd_train()
2057 set_rdqs(ch, rk, bl, x_center[ch][rk][bl]); in rd_train()
2060 set_vref(ch, bl, y_center[ch][bl]); in rd_train()
2084 uint8_t ch; /* channel counter */ in wr_train() local
2111 for (ch = 0; ch < NUM_CHANNELS; ch++) { in wr_train()
2112 if (mrc_params->channel_enables & (1 << ch)) { in wr_train()
2118 set_wdq(ch, rk, bl, ddr_wdq[PLATFORM_ID]); in wr_train()
2126 for (ch = 0; ch < NUM_CHANNELS; ch++) { in wr_train()
2127 if (mrc_params->channel_enables & (1 << ch)) { in wr_train()
2138 temp = get_wdqs(ch, rk, bl) - QRTR_CLK; in wr_train()
2139 delay[L][ch][rk][bl] = temp - QRTR_CLK; in wr_train()
2140 delay[R][ch][rk][bl] = temp + QRTR_CLK; in wr_train()
2164 for (ch = 0; ch < NUM_CHANNELS; ch++) { in wr_train()
2165 if (mrc_params->channel_enables & (1 << ch)) { in wr_train()
2172 set_wdq(ch, rk, bl, delay[side][ch][rk][bl]); in wr_train()
2180 for (ch = 0; ch < NUM_CHANNELS; ch++) { in wr_train()
2181 if (mrc_params->channel_enables & (1 << ch)) { in wr_train()
2186 address = get_addr(ch, rk); in wr_train()
2202 delay[L][ch][rk][bl] += WDQ_STEP; in wr_train()
2204 delay[R][ch][rk][bl] -= WDQ_STEP; in wr_train()
2207 if (delay[L][ch][rk][bl] != delay[R][ch][rk][bl]) { in wr_train()
2212 set_wdq(ch, rk, bl, in wr_train()
2213 delay[side][ch][rk][bl]); in wr_train()
2219 training_message(ch, rk, bl); in wr_train()
2234 for (ch = 0; ch < NUM_CHANNELS; ch++) { in wr_train()
2235 if (mrc_params->channel_enables & (1 << ch)) { in wr_train()
2246 delay[L][ch][rk][bl], in wr_train()
2247 delay[R][ch][rk][bl]); in wr_train()
2249 temp = (delay[R][ch][rk][bl] + delay[L][ch][rk][bl]) / 2; in wr_train()
2252 final_delay[ch][bl] += temp; in wr_train()
2253 set_wdq(ch, rk, bl, in wr_train()
2254 final_delay[ch][bl] / num_ranks_enabled); in wr_train()
2256 set_wdq(ch, rk, bl, temp); in wr_train()
2276 uint8_t ch, rk, bl; in store_timings() local
2279 for (ch = 0; ch < NUM_CHANNELS; ch++) { in store_timings()
2282 mt->rcvn[ch][rk][bl] = get_rcvn(ch, rk, bl); in store_timings()
2283 mt->rdqs[ch][rk][bl] = get_rdqs(ch, rk, bl); in store_timings()
2284 mt->wdqs[ch][rk][bl] = get_wdqs(ch, rk, bl); in store_timings()
2285 mt->wdq[ch][rk][bl] = get_wdq(ch, rk, bl); in store_timings()
2288 mt->vref[ch][bl] = get_vref(ch, bl); in store_timings()
2291 mt->wctl[ch][rk] = get_wctl(ch, rk); in store_timings()
2294 mt->wcmd[ch] = get_wcmd(ch); in store_timings()