282 	id1 = phy_read(phydev, MDIO_DEVAD_NONE, 2);  in board_eth_init()
283 	id2 = phy_read(phydev, MDIO_DEVAD_NONE, 3);  in board_eth_init()
331 	id1 = phy_read(phydev, MDIO_DEVAD_NONE, 2);  in mx6_rgmii_rework()
332 	id2 = phy_read(phydev, MDIO_DEVAD_NONE, 3);  in mx6_rgmii_rework()
336 		phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, 2);  in mx6_rgmii_rework()
337 		phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 4);  in mx6_rgmii_rework()
338 		phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_POST_INC_W | 0x2);  in mx6_rgmii_rework()
339 		phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0x0000);  in mx6_rgmii_rework()
341 		phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, 2);  in mx6_rgmii_rework()
342 		phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 5);  in mx6_rgmii_rework()
343 		phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_POST_INC_W | 0x2);  in mx6_rgmii_rework()
344 		phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, MII_KSZ9031_MOD_REG);  in mx6_rgmii_rework()
346 		phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, 2);  in mx6_rgmii_rework()
347 		phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 6);  in mx6_rgmii_rework()
348 		phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_POST_INC_W | 0x2);  in mx6_rgmii_rework()
349 		phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0xFFFF);  in mx6_rgmii_rework()
351 		phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, 2);  in mx6_rgmii_rework()
352 		phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 8);  in mx6_rgmii_rework()
353 		phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_POST_INC_W | 0x2);  in mx6_rgmii_rework()
354 		phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0x3FFF);  in mx6_rgmii_rework()
357 		phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, 0x0);  in mx6_rgmii_rework()
358 		phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0x4);  in mx6_rgmii_rework()
359 		phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_NO_POST_INC);  in mx6_rgmii_rework()
360 		phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0x6);  in mx6_rgmii_rework()
361 		phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_REG);  in mx6_rgmii_rework()
362 		phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0x3);  in mx6_rgmii_rework()
363 		phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_NO_POST_INC);  in mx6_rgmii_rework()
364 		phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0x1A80);  in mx6_rgmii_rework()
369 		phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, 0x7);  in mx6_rgmii_rework()
370 		phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, MII_KSZ9031_MOD_DATA_POST_INC_RW | 0x16);  in mx6_rgmii_rework()
371 		phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_NO_POST_INC | 0x7);  in mx6_rgmii_rework()
372 		val = phy_read(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA);  in mx6_rgmii_rework()
375 		phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, val);  in mx6_rgmii_rework()
378 		phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);  in mx6_rgmii_rework()
379 		val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);  in mx6_rgmii_rework()
381 		phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);  in mx6_rgmii_rework()
384 		phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0xb);  in mx6_rgmii_rework()
385 		val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);  in mx6_rgmii_rework()
386 		phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3c40);  in mx6_rgmii_rework()