Lines Matching refs:ODT
105 # bit2: 0, ODT control Rtt[0] (Rtt=2, 150 ohm termination)
107 # bit6: 1, ODT control Rtt[1] (Rtt=2, 150 ohm termination)
126 DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing
130 # bit15-12: 5, 5 cycles from read command to assertion of internal ODT signal
131 # bit19-16: 8, 8 cycles from read command to de-assertion of internal ODT signal
134 DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing
137 # bit15-12: 5, 5 cycles from write command to assertion of internal ODT signal
138 # bit19-16: 8, 8 cycles from write command to de-assertion of internal ODT signal
160 DATA 0xFFD01494 0x00030000 # DDR ODT Control (Low)
168 DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
169 # bit1-0: 0, M_ODT[0] assertion is controlled by ODT Control Low register
170 # bit3-2: 0, M_ODT[1] assertion is controlled by ODT Control Low register
173 DATA 0xFFD0149C 0x0000E803 # CPU ODT Control
174 # bit3-0: 0b0011, internal ODT is asserted during read from DRAM bank 0-1
175 # bit7-4: 0b0000, internal ODT is not asserted during write to DRAM bank 0-4
176 # bit9-8: 0, Internal ODT assertion is controlled by fiels
177 # bit11-10: 2, M_DQ, M_DM, and M_DQS I/O buffer ODT 75 ohm
178 # bit13-12: 2, M_STARTBURST_IN I/O buffer ODT 75 ohm
179 # bit14: 1, M_STARTBURST_IN ODT enabled
180 # bit15: 1, DDR IO ODT Unit: Drive ODT calibration values
181 # bit20-16: 0, Pad N channel driving strength for ODT
182 # bit25-21: 0, Pad P channel driving strength for ODT