Lines Matching +full:- +full:j4
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4 1.0 There are five Dual-In-Line Packages(DIP) Switches on MPC832XE SYS board
11 and some of those signals may be high-bit-number-0 too. Heed
17 SW3 is switch 18 as silk-screened onto the board.
28 SW3[1-8]= 0000_1000 (core PLL setting, core enable)
29 SW4[1-8]= 0001_0010 (Flash boot on local bus, system PLL setting)
30 SW5[1-8]= 0010_0110 (Boot from high end)
31 SW6[1-8]= 0011_0100 (Flash boot on 16 bit local bus)
32 SW7[1-8]= 1000_0011 (QE PLL setting)
35 J1 1-2 (ETH3_TXER)
36 J2 2-3 (MII mode)
37 J3 2-3 (MII mode)
38 J4 2-3 (ADSL clockOscillator)
39 J5 1-2 (ETH4_TXER)
40 J6 2-3 (ClockOscillator)
47 J1 1-2 (ETH3_TXER)
48 J2 1-2 (RMII mode)
49 J3 1-2 (RMII mode)
50 J4 2-3 (ADSL clockOscillator)
51 J5 1-2 (ETH4_TXER)
52 J6 2-3 (ClockOscillator)
67 0x9000_0000 0x9fff_ffff PCI MEM non-prefetch 256M
94 export CROSS_COMPILE=your-cross-compile-prefix
95 cd u-boot
100 MPC832x support PCI 33MHz and PCI 66MHz, to make U-Boot support PCI:
104 2)To Make U-Boot image support PCI 33MHz, use
107 3)To Make U-Boot image support PCI 66MHz, use
114 tftp 10000 u-boot.bin
116 5.1 Reflash U-Boot Image using U-Boot
118 tftp 20000 u-boot.bin