Lines Matching refs:SIUL2_MSCRn
20 mscr_offset_ck0 = SIUL2_MSCRn(_DDR0_CKE0); in lpddr2_config_iomux()
21 writel(LPDDR2_CLK0_PAD, SIUL2_MSCRn(_DDR0_CLK0)); in lpddr2_config_iomux()
23 writel(LPDDR2_CKEn_PAD, SIUL2_MSCRn(_DDR0_CKE0)); in lpddr2_config_iomux()
24 writel(LPDDR2_CKEn_PAD, SIUL2_MSCRn(_DDR0_CKE1)); in lpddr2_config_iomux()
26 writel(LPDDR2_CS_Bn_PAD, SIUL2_MSCRn(_DDR0_CS_B0)); in lpddr2_config_iomux()
27 writel(LPDDR2_CS_Bn_PAD, SIUL2_MSCRn(_DDR0_CS_B1)); in lpddr2_config_iomux()
30 writel(LPDDR2_DMn_PAD, SIUL2_MSCRn(i)); in lpddr2_config_iomux()
33 writel(LPDDR2_DQSn_PAD, SIUL2_MSCRn(i)); in lpddr2_config_iomux()
36 writel(LPDDR2_An_PAD, SIUL2_MSCRn(i)); in lpddr2_config_iomux()
39 writel(LPDDR2_Dn_PAD, SIUL2_MSCRn(i)); in lpddr2_config_iomux()
42 writel(LPDDR2_CLK0_PAD, SIUL2_MSCRn(_DDR1_CLK0)); in lpddr2_config_iomux()
44 writel(LPDDR2_CKEn_PAD, SIUL2_MSCRn(_DDR1_CKE0)); in lpddr2_config_iomux()
45 writel(LPDDR2_CKEn_PAD, SIUL2_MSCRn(_DDR1_CKE1)); in lpddr2_config_iomux()
47 writel(LPDDR2_CS_Bn_PAD, SIUL2_MSCRn(_DDR1_CS_B0)); in lpddr2_config_iomux()
48 writel(LPDDR2_CS_Bn_PAD, SIUL2_MSCRn(_DDR1_CS_B1)); in lpddr2_config_iomux()
51 writel(LPDDR2_DMn_PAD, SIUL2_MSCRn(i)); in lpddr2_config_iomux()
54 writel(LPDDR2_DQSn_PAD, SIUL2_MSCRn(i)); in lpddr2_config_iomux()
57 writel(LPDDR2_An_PAD, SIUL2_MSCRn(i)); in lpddr2_config_iomux()
60 writel(LPDDR2_Dn_PAD, SIUL2_MSCRn(i)); in lpddr2_config_iomux()