54 	writel(SIUL2_UART_TXD, SIUL2_MSCRn(SIUL2_UART0_TXD_PAD));  in setup_iomux_uart()
57 	writel(SIUL2_UART_MSCR_RXD, SIUL2_MSCRn(SIUL2_UART0_MSCR_RXD_PAD));  in setup_iomux_uart()
95 	writel(SIUL2_USDHC_PAD_CTRL_CLK, SIUL2_MSCRn(150));  in board_mmc_init()
96 	writel(0x3, SIUL2_MSCRn(902));  in board_mmc_init()
99 	writel(SIUL2_USDHC_PAD_CTRL_CMD, SIUL2_MSCRn(151));  in board_mmc_init()
100 	writel(0x3, SIUL2_MSCRn(901));  in board_mmc_init()
103 	writel(SIUL2_USDHC_PAD_CTRL_DAT0_3, SIUL2_MSCRn(152));  in board_mmc_init()
104 	writel(0x3, SIUL2_MSCRn(903));  in board_mmc_init()
107 	writel(SIUL2_USDHC_PAD_CTRL_DAT0_3, SIUL2_MSCRn(153));  in board_mmc_init()
108 	writel(0x3, SIUL2_MSCRn(904));  in board_mmc_init()
111 	writel(SIUL2_USDHC_PAD_CTRL_DAT0_3, SIUL2_MSCRn(154));  in board_mmc_init()
112 	writel(0x3, SIUL2_MSCRn(905));  in board_mmc_init()
115 	writel(SIUL2_USDHC_PAD_CTRL_DAT0_3, SIUL2_MSCRn(155));  in board_mmc_init()
116 	writel(0x3, SIUL2_MSCRn(906));  in board_mmc_init()
119 	writel(SIUL2_USDHC_PAD_CTRL_DAT4_7, SIUL2_MSCRn(159));  in board_mmc_init()
120 	writel(0x3, SIUL2_MSCRn(907));  in board_mmc_init()
123 	writel(SIUL2_USDHC_PAD_CTRL_DAT4_7, SIUL2_MSCRn(160));  in board_mmc_init()
124 	writel(0x3, SIUL2_MSCRn(908));  in board_mmc_init()
127 	writel(SIUL2_USDHC_PAD_CTRL_DAT4_7, SIUL2_MSCRn(161));  in board_mmc_init()
128 	writel(0x3, SIUL2_MSCRn(909));  in board_mmc_init()
131 	writel(SIUL2_USDHC_PAD_CTRL_DAT4_7, SIUL2_MSCRn(162));  in board_mmc_init()
132 	writel(0x3, SIUL2_MSCRn(910));  in board_mmc_init()