Lines Matching refs:MODE

16 	{OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)},  /* UART0_RXD */
17 	{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},              /* UART0_TXD */
22 	{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)},  /* MMC0_DAT3 */
23 	{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)},  /* MMC0_DAT2 */
24 	{OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)},  /* MMC0_DAT1 */
25 	{OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)},  /* MMC0_DAT0 */
26 	{OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)},   /* MMC0_CLK */
27 	{OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)},   /* MMC0_CMD */
28 	{OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)},   /* MMC0_CD */
34 	{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
36 	{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
41 	{OFFSET(mii1_txen), MODE(2)},                   /* RGMII1_TCTL */
42 	{OFFSET(mii1_rxdv), MODE(2) | RXACTIVE},        /* RGMII1_RCTL */
43 	{OFFSET(mii1_txd3), MODE(2)},                   /* RGMII1_TD3 */
44 	{OFFSET(mii1_txd2), MODE(2)},                   /* RGMII1_TD2 */
45 	{OFFSET(mii1_txd1), MODE(2)},                   /* RGMII1_TD1 */
46 	{OFFSET(mii1_txd0), MODE(2)},                   /* RGMII1_TD0 */
47 	{OFFSET(mii1_txclk), MODE(2)},                  /* RGMII1_TCLK */
48 	{OFFSET(mii1_rxclk), MODE(2) | RXACTIVE},       /* RGMII1_RCLK */
49 	{OFFSET(mii1_rxd3), MODE(2) | RXACTIVE},        /* RGMII1_RD3 */
50 	{OFFSET(mii1_rxd2), MODE(2) | RXACTIVE},        /* RGMII1_RD2 */
51 	{OFFSET(mii1_rxd1), MODE(2) | RXACTIVE},        /* RGMII1_RD1 */
52 	{OFFSET(mii1_rxd0), MODE(2) | RXACTIVE},        /* RGMII1_RD0 */
53 	{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
54 	{OFFSET(mdio_clk), MODE(0) | PULLUP_EN},        /* MDIO_CLK */
55 	{OFFSET(rmii1_refclk), MODE(7) | RXACTIVE},     /* ETH_INT */
56 	{OFFSET(mii1_col), MODE(7) | PULLUP_EN},        /* PHY_NRESET */
57 	{OFFSET(xdma_event_intr1), MODE(3)},