Lines Matching refs:PCI_SIZE_16

36 	case PCI_SIZE_16:  in pci_byte_size()
73 	case PCI_SIZE_16:  in pci_read_config()
167 	{ "vendor ID", PCI_SIZE_16, PCI_VENDOR_ID },
168 	{ "device ID", PCI_SIZE_16, PCI_DEVICE_ID },
169 	{ "command register ID", PCI_SIZE_16, PCI_COMMAND },
170 	{ "status register", PCI_SIZE_16, PCI_STATUS },
193 	{ "sub system vendor ID", PCI_SIZE_16, PCI_SUBSYSTEM_VENDOR_ID },
194 	{ "sub system ID", PCI_SIZE_16, PCI_SUBSYSTEM_ID },
211 	{ "secondary status", PCI_SIZE_16, PCI_SEC_STATUS },
212 	{ "memory base", PCI_SIZE_16, PCI_MEMORY_BASE },
213 	{ "memory limit", PCI_SIZE_16, PCI_MEMORY_LIMIT },
214 	{ "prefetch memory base", PCI_SIZE_16, PCI_PREF_MEMORY_BASE },
215 	{ "prefetch memory limit", PCI_SIZE_16, PCI_PREF_MEMORY_LIMIT },
218 	{ "IO base upper 16 bits", PCI_SIZE_16, PCI_IO_BASE_UPPER16 },
219 	{ "IO limit upper 16 bits", PCI_SIZE_16, PCI_IO_LIMIT_UPPER16 },
223 	{ "bridge control", PCI_SIZE_16, PCI_BRIDGE_CONTROL },
229 	{ "secondary status", PCI_SIZE_16, PCI_CB_SEC_STATUS },
238 	{ "CardBus IO base 0", PCI_SIZE_16, PCI_CB_IO_BASE_0 },
239 	{ "CardBus IO base high 0", PCI_SIZE_16, PCI_CB_IO_BASE_0_HI },
240 	{ "CardBus IO limit 0", PCI_SIZE_16, PCI_CB_IO_LIMIT_0 },
241 	{ "CardBus IO limit high 0", PCI_SIZE_16, PCI_CB_IO_LIMIT_0_HI },
242 	{ "CardBus IO base 1", PCI_SIZE_16, PCI_CB_IO_BASE_1 },
243 	{ "CardBus IO base high 1", PCI_SIZE_16, PCI_CB_IO_BASE_1_HI },
244 	{ "CardBus IO limit 1", PCI_SIZE_16, PCI_CB_IO_LIMIT_1 },
245 	{ "CardBus IO limit high 1", PCI_SIZE_16, PCI_CB_IO_LIMIT_1_HI },
248 	{ "bridge control", PCI_SIZE_16, PCI_CB_BRIDGE_CONTROL },
249 	{ "subvendor ID", PCI_SIZE_16, PCI_CB_SUBSYSTEM_VENDOR_ID },
250 	{ "subdevice ID", PCI_SIZE_16, PCI_CB_SUBSYSTEM_ID },
322 	dm_pci_read_config(dev, PCI_VENDOR_ID, &vendor, PCI_SIZE_16);  in pci_header_show_brief()
323 	dm_pci_read_config(dev, PCI_DEVICE_ID, &device, PCI_SIZE_16);  in pci_header_show_brief()